Philips
Semiconductors
PHILIPS
DATA SHEET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4028B
MSI
1-of-10 decoder
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
10 13 12 11
DECODER
00 01 02 03 04 05 06 O7 08 09
3 14 2 15 1 6 7 4 9 5
127mm
I6 ‘5 u u ‘2 u m a
Van 03 0‘ A‘ A2 A3 A0 03
D HEF40288
0L 02 on 07 09 05 06 Vss
123u557a
new;
January 1995 2
Philips Semiconductors Product specification
1-of-10 decoder HEF4028B
MSI
DESCRIPTION
The HEF4028B is a 4-bit BCD to 1-of-10 active HIGH
decoder. A 1-2-4-8 BCD code applied to inputs A0 to A3
causes the selected output to be HIGH, the other nine will
be LOW. If desired, the device may be used as a 1-of-8
decoder with enable; 3-bit octal inputs are applied to inputs
A0, A1 and A2 selecting an output O0 to O7. Input A3 then
becomes an active LOW enable, forcing the selected
output LOW when A3 is HIGH. The HEF4028B may also
be used as an 8-output (O0 to O7) demultiplexer with A0 to
A2 as address inputs and A3 as an active LOW data input.
The outputs are fully buffered for best performance.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF4028BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4028BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4028BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
A0to A3address inputs, 1-2-4-8 BCD
O0to O9outputs (active HIGH)
22222222222
0 0 0 0 0 O O O 0 O 0,
6
January 1995 3
Philips Semiconductors Product specification
1-of-10 decoder HEF4028B
MSI
Fig.3 Logic diagram.
January 1995 4
Philips Semiconductors Product specification
1-of-10 decoder HEF4028B
MSI
TRUTH TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
2. Extraordinary states.
INPUTS OUTPUTS
A3A2A1A0O0O1O2O3O4O5O6O7O8O9
LLLL H LLLLLLLLL
LLLH L HLLLLLLLL
LLHL L LHLLLLLLL
LLHH L LLHLLLLLL
LHLL L L LLHLLLLL
LHLH L L LLLHLLLL
LHHL L L LLLLHLLL
LHHH L L LLLLLHLL
HLLL L L LLLLLLHL
HLLH L L LLLLLLLH
HLHL L L LLLLLLLL
(2)
HLHH L L LLLLLLLL
HHL L L L LLLLL LL L
HHLH L L LLLLL LL L
HHHL L L LLLLL LL L
HHHH L L LLLLL LL L
January 1995 5
Philips Semiconductors Product specification
1-of-10 decoder HEF4028B
MSI
AC CHARACTERISTICS
VSS =0V; T
amb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
An→On5
tPHL
100 200 ns 73 ns +(0,55 ns/pF) CL
HIGH to LOW 10 40 80 ns 29 ns +(0,23 ns/pF) CL
15 30 60 ns 22 ns +(0,16 ns/pF) CL
5
tPLH
90 180 ns 63 ns +(0,55 ns/pF) CL
LOW to HIGH 10 40 80 ns 29 ns +(0,23 ns/pF) CL
15 30 60 ns 22 ns +(0,16 ns/pF) CL
Output transition times 5
tTHL
60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 350 fi+∑(foCL) ×VDD 2where
dissipation per 10 2 200 fi+∑(foCL) ×VDD 2fi= input freq. (MHz)
package (P) 15 7 350 fi+∑(foCL) ×VDD 2fo= output freq. (MHz)
CL= total load cap. (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
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