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MX25L12835F

P/N: PM1795

MX25L12835F

3V, 128M-BIT [x 1/x 2/x 4]

CMOS MXSMIO® (SERIAL MULTI I/O)

FLASH MEMORY

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Contents

1. FEATURES ..............................................................................................................................................................4

2. GENERAL DESCRIPTION ..................................................................................................................................... 6

Table 1. Read performance Comparison ....................................................................................................6

3. PIN CONFIGURATIONS ......................................................................................................................................... 7

4. PIN DESCRIPTION .................................................................................................................................................. 7

5. BLOCK DIAGRAM ................................................................................................................................................... 8

6. DATA PROTECTION ................................................................................................................................................ 9

Table 2. Protected Area Sizes ...................................................................................................................10

Table 3. 4K-bit Secured OTP Definition .................................................................................................... 11

7. Memory Organization ........................................................................................................................................... 12

Table 4. Memory Organization ..................................................................................................................12

8. DEVICE OPERATION ............................................................................................................................................ 13

8-1. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 15

9. COMMAND DESCRIPTION ................................................................................................................................... 16

Table 5. Command Set ..............................................................................................................................16

9-1. Write Enable (WREN) .............................................................................................................................. 20

9-2. Write Disable (WRDI) ............................................................................................................................... 21

9-3. Read Identification (RDID) ....................................................................................................................... 22

9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 23

9-5. Read Electronic Manufacturer ID & Device ID (REMS) ........................................................................... 25

9-6. QPI ID Read (QPIID) ............................................................................................................................... 26

Table 6. ID Definitions ..............................................................................................................................26

9-7. Read Status Register (RDSR) ................................................................................................................. 27

9-8. Read Configuration Register (RDCR) ...................................................................................................... 28

Table 7. Configuration Register Table .......................................................................................................32

9-9. Write Status Register (WRSR) ................................................................................................................. 34

Table 8. Protection Modes .........................................................................................................................35

9-10. Read Data Bytes (READ) ........................................................................................................................ 38

9-11. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 39

9-12. Dual Output Read Mode (DREAD) .......................................................................................................... 40

9-13. 2 x I/O Read Mode (2READ) ................................................................................................................... 41

9-14. Quad Read Mode (QREAD) .................................................................................................................... 42

9-15. 4 x I/O Read Mode (4READ) ................................................................................................................... 43

9-16. Burst Read ............................................................................................................................................... 45

9-17. Performance Enhance Mode ................................................................................................................... 46

9-18. Fast Boot ................................................................................................................................................. 49

9-19. Sector Erase (SE) .................................................................................................................................... 52

9-20. Block Erase (BE32K) ............................................................................................................................... 53

9-21. Block Erase (BE) ..................................................................................................................................... 54

9-22. Chip Erase (CE) ....................................................................................................................................... 55

9-23. Page Program (PP) ................................................................................................................................. 56

9-24. 4 x I/O Page Program (4PP) .................................................................................................................... 58

9-25. Deep Power-down (DP) ........................................................................................................................... 59

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-26. Enter Secured OTP (ENSO) .................................................................................................................... 60

9-27. Exit Secured OTP (EXSO) ....................................................................................................................... 60

9-28. Read Security Register (RDSCUR) ......................................................................................................... 60

9-29. Write Security Register (WRSCUR) ......................................................................................................... 60

Table 9. Security Register Definition .........................................................................................................61

9-30. Write Protection Selection (WPSEL) ........................................................................................................ 62

9-31. Advanced Sector Protection .................................................................................................................... 64

9-32. Password Protection Mode ...................................................................................................................... 71

9-33. Program/Erase Suspend/Resume ........................................................................................................... 73

9-34. Erase Suspend ........................................................................................................................................ 73

9-35. Program Suspend .................................................................................................................................... 73

9-36. Write-Resume .......................................................................................................................................... 75

9-37. No Operation (NOP) ................................................................................................................................ 75

9-38. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 75

9-39. Read SFDP Mode (RDSFDP) .................................................................................................................. 77

Table 10. Signature and Parameter Identification Data Values ................................................................ 78

Table 11. Parameter Table (0): JEDEC Flash Parameter Tables ..............................................................79

Table 12. Parameter Table (1): Macronix Flash Parameter Tables ...........................................................81

10. RESET.................................................................................................................................................................. 83

Table 13. Reset Timing-(Power On) ..........................................................................................................83

Table 14. Reset Timing-(Other Operation) ................................................................................................83

11. POWER-ON STATE ............................................................................................................................................. 84

12. ELECTRICAL SPECIFICATIONS ........................................................................................................................ 85

Table 15. ABSOLUTE MAXIMUM RATINGS ............................................................................................85

Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz .................................................................................... 85

Table 17. DC CHARACTERISTICS .........................................................................................................87

Table 18. AC CHARACTERISTICS ......................................................................................................... 88

13. OPERATING CONDITIONS ................................................................................................................................. 90

Table 19. Power-Up/Down Voltage and Timing ......................................................................................... 92

13-1. INITIAL DELIVERY STATE ...................................................................................................................... 92

14. ERASE AND PROGRAMMING PERFORMANCE .............................................................................................. 93

15. DATA RETENTION .............................................................................................................................................. 93

16. LATCH-UP CHARACTERISTICS ........................................................................................................................ 93

17. ORDERING INFORMATION ................................................................................................................................ 94

18. PART NAME DESCRIPTION ............................................................................................................................... 95

19. PACKAGE INFORMATION .................................................................................................................................. 96

19-1. 8-pin SOP (200mil) .................................................................................................................................. 96

19-2. 16-pin SOP (300mil) ................................................................................................................................ 97

19-3. 8-land WSON (6x5mm)............................................................................................................................ 98

19-4. 8-land WSON (8x6mm)............................................................................................................................ 99

20. REVISION HISTORY ......................................................................................................................................... 100

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

1. FEATURES

GENERAL

• Supports Serial Peripheral Interface -- Mode 0 and Mode 3

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program operations

• 128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two I/O mode) structure or 33,554,432 x 4 bits (four

I/O mode) structure

• Protocol Support

- Single I/O, Dual I/O and Quad I/O

• Latch-up protected to 100mA from -1V to Vcc +1V

• Fast read for SPI mode

- Support clock frequency up to 133MHz for all protocols

- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions.

- Configurable dummy cycle number for fast read operation

• Quad Peripheral Interface (QPI) available

• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each

- Any Block can be erased individually

• Programming :

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance program performance

• Typical 100,000 erase/program cycles

• 20 years data retention

SOFTWARE FEATURES

• Input Data Format

- 1-byte Command code

• Advanced Security Features

- Block lock protection

The BP0-BP3 and T/B status bit defines the size of the area to be protection against program and erase instruc-

tions

- Advanced sector protection function (Solid and Password Protect)

• Additional 4K bit security OTP

- Features unique identifier

- factory locked identifiable, and customer lockable

• Command Reset

• Program/Erase Suspend and Resume operation

• Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and 1-byte device ID

• Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES

• SCLK Input

- Serial clock input

• SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

3V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O)

FLASH MEMORY

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

• SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

• WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

• RESET#/SIO3

- Hardware Reset pin or Serial input & Output for 4 x I/O read mode

• PACKAGE

-8-pin SOP (200mil)

-16-pin SOP (300mil)

-8-land WSON (6x5mm)

-8-land WSON (8x6mm)

- All devices are RoHS Compliant and Halogen-free

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

2. GENERAL DESCRIPTION

MX25L12835F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in

two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. MX25L12835F feature a

serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O

mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial

access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-

put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin,

SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25L12835F

MXSMIO (Serial Multi I/O)

provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-

fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25L12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read performance Comparison

Numbers of

Dummy Cycles

Fast Read

(MHz)

Dual Output

Fast Read

(MHz)

Quad Output

Fast Read

(MHz)

Dual IO

Fast Read

(MHz)

Quad IO

Fast Read

(MHz)

4 - - - 84* 70

6 104 104 84 104 84*

8 104* 104* 104* 104 104

10 133 133 133 133 133

Note: * mean default status

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

3. PIN CONFIGURATIONS 4. PIN DESCRIPTION

SYMBOL DESCRIPTION

CS# Chip Select

SI/SIO0

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/O

read mode)

SO/SIO1

Serial Data Output (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or 4xI/O

read mode)

SCLK Clock Input

WP#/SIO2

Write protection Active low or Serial

Data Input & Output (for 4xI/O read

mode)

RESET#/SIO3

Hardware Reset Pin Active low or

Serial Data Input & Output (for 4xI/O

read mode)

VCC + 3V Power Supply

GND Ground

NC No Connection

DNU Do not use

16-PIN SOP (300mil)

DNU/SIO3

VCC

RESET#

CS#

SO/SIO1

SCLK

SI/SIO0

GND

WP#/SIO2

8-WSON (6x5mm, 8x6mm)

CS#

SO/SIO1

WP#/SIO2

GND

VCC

RESET#/SIO3

SCLK

SI/SIO0

8-PIN SOP (200mil)

CS#

SO/SIO1

WP#/SIO2

GND

VCC

RESET#/SIO3

SCLK

SI/SIO0

Notes:

1. RESET# pin has internal pull up.

2. When using 1I/O or 2I/O (QE bit not enable), the

DNU/SIO3 pin of 16SOP can not connect to GND.

Recommend to connect this pin to VCC or floating.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

5. BLOCK DIAGRAM

Address

Generator

Memory Array

Y-Decoder

X-Decoder

Data

SRAM

Buffer

SI/SIO0

SO/SIO1

SIO2 *

SIO3 *

WP# *

HOLD# *

RESET# *

CS#

SCLK Clock Generator

State

Machine

Mode

Logic

Sense

Amplifier

Generator

Output

Buffer

* Depends on part number options.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-

nature command (RES), and softreset command.

• Advanced Security Features: there are some protection and security features which protect content from inad-

vertent write and hostile access.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 2. Protected Area Sizes

Status bit Protect Level

BP3 BP2 BP1 BP0 128Mb

0 0 0 0 0 (none)

0 0 0 1 1 (1 block, protected block 255th)

00102 (2 blocks, block 254th-255th)

00113 (4 blocks, block 252nd-255th)

01004 (8 blocks, block 248th-255th)

01015 (16 blocks, block 240th-255th)

01106 (32 blocks, block 224th-255th)

01117 (64 blocks, block 192nd-255th)

10008 (128 blocks, block 128th-255th)

1 0 0 1 9 (256 blocks, protected all)

1 0 1 0 10 (256 blocks, protected all)

1 0 1 1 11 (256 blocks, protected all)

1 1 0 0 12 (256 blocks, protected all)

1 1 0 1 13 (256 blocks, protected all)

1 1 1 0 14 (256 blocks, protected all)

1 1 1 1 15 (256 blocks, protected all)

Status bit Protect Level

BP3 BP2 BP1 BP0 128Mb

0 0 0 0 0 (none)

0 0 0 1 1 (1 block, protected block 0th)

0 0 1 0 2 (2 blocks, protected block 0th~1st)

0 0 1 1 3 (4 blocks, protected block 0th~3rd)

0 1 0 0 4 (8 blocks, protected block 0th~7th)

0 1 0 1 5 (16 blocks, protected block 0th~15th)

0 1 1 0 6 (32 blocks, protected block 0th~31st)

0 1 1 1 7 (64 blocks, protected block 0th~63rd)

1 0 0 0 8 (128 blocks, protected block 0th~127th)

1 0 0 1 9 (256 blocks, protected all)

1 0 1 0 10 (256 blocks, protected all)

1 0 1 1 11 (256 blocks, protected all)

1 1 0 0 12 (256 blocks, protected all)

1 1 0 1 13 (256 blocks, protected all)

1 1 1 0 14 (256 blocks, protected all)

1 1 1 1 15 (256 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Protected Area Sizes (T/B bit = 0)

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be

protected as read only. The protected area definition is shown as Table 2. Protected Area Sizes, the protected

areas are more flexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Reg-

ister Write Protect bit.

- In four I/O and QPI mode, the feature of HPM will be disabled.

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MX25L12835F

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II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting de-

vice unique serial number - Which may be set by factory or system customer.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),

and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security

OTP command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-

mand to set customer lock-down bit1 as "1". Please refer to Table 9. Security Register Definition for security reg-

ister bit definition and Table 3. 4K-bit Secured OTP Definition for address range definition.

- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured

OTP mode, array access is not allowed.

Table 3. 4K-bit Secured OTP Definition

Address range Size Standard Factory Lock Customer Lock

xxx000~xxx00F 128-bit ESN (electrical serial number) Determined by customer

xxx010~xxx1FF 3968-bit N/A

MEI—II: MACRDNIX INTERVATIONAL Co., LTD. B1ock(e4k.0y:e) Block(32K-byte) Sector Address Range 4095 FFFOOOh FFFFFFh 1 v 4033 FFBOOOh FFSFFFh 4037 FF7000h FF7FFFh A 4030 FFDDOOh FFOFFFh 3 1 4079 FEFOOOh FEFFFFh 4072 FEBOOOh FESFFFh ; 4074 FE7000h FE7FFFh 4064 FEOOOOh FEOFFFh 4063 FDFOOOh FDFFFFh 4055 FD7000h FD7FFFh 4043 women FDOFFFh 47 OZFOOOh OZFFFFh 40 OZBOOOh OZSFFFh 39 027000n 027FFFh 32 02000011 OZOFFFh 31 mF000h 01FFFFh A 1 23 m7000n 017FFFh 1 16 04000011 mOFFFh 15 OOFDOOh DDFFFFh 1 v 7 00700011 007FFFh A 0 0000mm OOOFFFh 1

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 4. Memory Organization

7. Memory Organization

Block(32K-byte) Sector

4095 FFF000h FFFFFFh

…

4088 FF8000h FF8FFFh

4087 FF7000h FF7FFFh

…

4080 FF0000h FF0FFFh

4079 FEF000h FEFFFFh

…

4072 FE8000h FE8FFFh

4071 FE7000h FE7FFFh

…

4064 FE0000h FE0FFFh

4063 FDF000h FDFFFFh

…

4056 FD8000h FD8FFFh

4055 FD7000h FD7FFFh

…

4048 FD0000h FD0FFFh

47 02F000h 02FFFFh

…

40 028000h 028FFFh

39 027000h 027FFFh

…

32 020000h 020FFFh

31 01F000h 01FFFFh

…

24 018000h 018FFFh

23 017000h 017FFFh

…

16 010000h 010FFFh

15 00F000h 00FFFFh

…

8008000h 008FFFh

7007000h 007FFFh

…

0000000h 000FFFh

508

507

506

Address Range

511

510

509

individual block

lock/unlock unit:64K-byte

individual 16 sectors

lock/unlock unit:4K-byte

individual block

lock/unlock unit:64K-byte

individual block

lock/unlock unit:64K-byte

Block(64K-byte)

253

255

254

individual 16 sectors

lock/unlock unit:4K-byte

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-

eration.

2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby

mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.

3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode

until next CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as Figure 1. Serial Modes Supported.

5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, DREAD, 4READ, QREAD,

RDSFDP, RES, REMS, QPIID, RDDPB, RDSPB, RDPASS, RDLR, RDFBR, RDSPBLK, RDCR the shifted-in

instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be

high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO,

WRSCUR, WPSEL, GBLK, GBULK, SPBLK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the

CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is ne-

glected and will not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

SCLK

MSB

CPHA shift in shift out

CPOL

0(Serial mode 0)

(Serial mode 3) 1

SCLK

MSB

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 2. Serial Input Timing

Figure 3. Output Timing

SCLK

CS#

MSB

tDVCH

High-Z

LSB

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

LSB

ADDR.LSB IN

tSHQZ

tCH

tCL

tCLQX

tCLQV

tCLQX

tCLQV

SCLK

CS#

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

8-1. Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in

command cycles, address cycles and as well as data output cycles.

Enable QPI mode

By issuing EQIO command (35h), the QPI mode is enable. After QPI mode has been enabled, the device enter quad

mode (4-4-4) without QE bit status changed.

Figure 4. Enable QPI Sequence

MODE 3

SCLK

SIO0

CS#

MODE 0

234567

35h

SIO[3:1]

0 1

Reset QPI (RSTQIO)

To reset the QPI mode, the RSTQIO (F5h) command is required. After the RSTQIO command is issued, the device

returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).

Note:

For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL (as defined in Table 18. AC

CHARACTERISTICS) for next instruction.

Figure 5. Reset QPI Mode

SCLK

SIO[3:0]

CS#

F5h

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MX25L12835F

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9. COMMAND DESCRIPTION

Table 5. Command Set

Read/Write Array Commands

Command

(byte)

READ

(normal read)

FAST READ

(fast read data)

2READ

(2 x I/O read

command)

DREAD

(1I 2O read)

4READ

(4 I/O read)

QREAD

(1I 4O read)

Mode SPI SPI SPI SPI SPI/QPI SPI

Address Bytes 333333

1st byte 03 (hex) 0B (hex) BB (hex) 3B (hex) EB (hex) 6B (hex)

2nd byte ADD1 ADD1 ADD1 ADD1 ADD1 ADD1

3rd byte ADD2 ADD2 ADD2 ADD2 ADD2 ADD2

4th byte ADD3 ADD3 ADD3 ADD3 ADD3 ADD3

5th byte Dummy* Dummy* Dummy* Dummy* Dummy*

Data Cycles

Action

n bytes read out

until CS# goes

high

n bytes read out

until CS# goes

high

n bytes read out

by 2 x I/O until

CS# goes high

n bytes read out

by Dual output

until CS# goes

high

n bytes read out

by 4 x I/O until

CS# goes high

n bytes read out

by Quad output

until CS# goes

high

Command

(byte)

(page program)

4PP

(quad page

program)

(sector erase)

BE 32K

(block erase

32KB)

(block erase

64KB)

(chip erase)

Mode SPI/QPI SPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI

Address Bytes 333330

1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) D8 (hex) 60 or C7 (hex)

2nd byte ADD1 ADD1 ADD1 ADD1

3rd byte ADD2 ADD2 ADD2 ADD2

4th byte ADD3 ADD3 ADD3 ADD3

5th byte

Data Cycles 1-256 1-256

Action

to program the

selected page

quad input to

program the

selected page

to erase the

selected sector

to erase the

selected 32K

block

to erase the

selected block

to erase whole

chip

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Command

(byte)

WREN

(write enable)

WRDI

(write disable)

RDSR

(read status

RDCR

(read

configuration

WRSR

(write status/

configuration

WPSEL

(Write Protect

Selection)

EQIO

(Enable QPI)

Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI

1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 68 (hex) 35 (hex)

2nd byte Values

3rd byte Values

4th byte

5th byte

Data Cycles 1-2

Action

sets the (WEL)

write enable

latch bit

resets the

(WEL) write

enable latch bit

to read out the

values of the

status register

to read out the

values of the

configuration

to write new

values of the

status/

configuration

to enter and

enable individal

block protect

mode

Entering the

QPI mode

Command

(byte)

RSTQIO

(Reset QPI)

PGM/ERS

Suspend

(Suspends

Program/

Erase)

PGM/ERS

Resume

(Resumes

Program/

Erase)

DP (Deep

power down)

RDP (Release

from deep

power down)

SBL

(Set Burst

Length)

RDFBR

(read fast boot

Mode QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI

1st byte F5 (hex) B0 (hex) 30 (hex) B9 (hex) AB (hex) C0 (hex) 16(hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles 1-4

Action

Exiting the QPI

mode

enters deep

power down

mode

release from

deep power

down mode

to set Burst

length

Command

(byte)

WRFBR

(write fast boot

ESFBR

(erase fast

boot register)

Mode SPI SPI

1st byte 17(hex) 18(hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles 4

Action

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ID/Security Commands

Command

(byte)

RDID

(read identific-

ation)

RES

(read electronic

ID)

REMS

(read electronic

manufacturer &

device ID)

QPIID

(QPI ID

Read)

RDSFDP

ENSO

(enter secured

OTP)

EXSO

(exit secured

OTP)

Mode SPI SPI/QPI SPI QPI SPI/QPI SPI/QPI SPI/QPI

Address Bytes 0 0 0 0 3 0 0

1st byte 9F (hex) AB (hex) 90 (hex) AF (hex) 5A (hex) B1 (hex) C1 (hex)

2nd byte x x ADD1

3rd byte x x ADD2

4th byte x ADD1(Note 2) ADD3

5th byte Dummy(8)(Note 4)

Action

outputs JEDEC

ID: 1-byte

Manufacturer

ID & 2-byte

Device ID

to read out

1-byte Device

output the

Manufacturer

ID & Device ID

ID in QPI

interface

Read SFDP

mode

to enter the

4K-bit secured

OTP mode

to exit the

4K-bit secured

OTP mode

Command

(byte)

RDSCUR

(read security

WRSCUR

(write

security

GBLK

(gang block

lock)

GBULK

(gang block

unlock)

WRLR

(write Lock

RDLR

(read Lock

WRPASS

(write

password

RDPASS

(read

password

Mode SPI/QPI SPI/QPI SPI/QPI SPI/QPI SPI SPI SPI SPI

Address Bytes 00000000

1st byte 2B (hex) 2F (hex) 7E (hex) 98 (hex) 2C (hex) 2D (hex) 28 (hex) 27 (hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles 2 2 1-8 1-8

Action

to read value

of security

to set the

lock-down bit

as "1" (once

lock-down,

cannot be

updated)

whole chip

write protect

whole chip

unprotect

Command

(byte)

PASSULK

(password

unlock)

WRSPB

(SPB bit

program)

ESSPB

(all SPB bit

erase)

RDSPB

(read SPB

status)

SPBLK

(SPB lock

set)

RDSPBLK

(SPB lock

WRDPB

(write DPB

RDDPB

(read DPB

Mode SPI SPI SPI SPI SPI SPI SPI SPI

Address Bytes 04040044

1st byte 29 (hex) E3 (hex) E4 (hex) E2 (hex) A6 (hex) A7 (hex) E1 (hex) E0 (hex)

2nd byte ADD1 ADD1 ADD1 ADD1

3rd byte ADD2 ADD2 ADD2 ADD2

4th byte ADD3 ADD3 ADD3 ADD3

5th byte ADD4 ADD4 ADD4 ADD4

Data Cycles 8 1 2 1 1

Action

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Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-

den mode.

Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.

Note 3: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the

reset operation will be disabled.

Note 4: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)"

represents there are 8 clock cycles for the data in.

Reset Commands

Command

(byte)

NOP

(No Operation)

RSTEN

(Reset Enable)

RST

(Reset

Memory)

Mode SPI/QPI SPI/QPI SPI/QPI

1st byte 00 (hex) 66 (hex) 99 (hex)

2nd byte

3rd byte

4th byte

5th byte

Action (Note 3)

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9-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,

SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time

after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

Figure 6. Write Enable (WREN) Sequence (SPI Mode)

21 34567

High-Z

06h

Command

SCLK

CS#

Mode 3

Mode 0

Figure 7. Write Enable (WREN) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

06h

0 1

Command

Mode 3

Mode 0

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9-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

The WEL bit is reset by following situations:

- Power-up

- Reset# pin driven low

- WRDI command completion

- WRSR command completion

- PP command completion

- 4PP command completion

- SE command completion

- BE32K command completion

- BE command completion

- CE command completion

- PGM/ERS Suspend command completion

- Softreset command completion

- WRSCUR command completion

- WPSEL command completion

- GBLK command completion

- GBULK command completion

- WRLR command completion

- WRPASS command completion

- PASSULK command completion

- SPBLK command completion

- WRSPB command completion

- ESSPB command completion

- WRDPB command completion

- WRFBR command completion

- ESFBR command completion

Figure 8. Write Disable (WRDI) Sequence (SPI Mode)

21 34567

High-Z

0Mode 3

Mode 0

04h

Command

SCLK

CS#

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9-3. Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macro-

nix Manufacturer ID and Device ID are listed as Table 6. ID Definitions.

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out

on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Figure 10. Read Identification (RDID) Sequence (SPI mode only)

21 3456789

Command

Manufacturer Identification

High-Z

MSB

15 14 13 3210

Device Identification

MSB

7 6 5 2 1 0

16 17 18 28 29 30 31

SCLK

CS#

9Fh

Mode 3

Mode 0

14 15

10 13

Figure 9. Write Disable (WRDI) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

04h

0 1

Command

Mode 3

Mode 0

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9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in

the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip

Select (CS#) must remain High for at least tRES2(max), as specified in Table 18. AC CHARACTERISTICS. Once in

the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

The RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash

from deep power down mode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6. ID

Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,

please use RDID instruction.

Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in

progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-

edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously

in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in

Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode)

21 3456789 10 28 29 30 31 32 33 34 35

22 21 3210

36 37 38

765432 0

High-Z Electronic Signature Out

3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

SCLK

CS#

ABh

Command

Mode 3

Mode 0

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SCLK

SIO[3:0]

CS#

MODE 0

MODE 3

MSB LSB

Data Out

Data In

H0XXXXXX L0

Deep Power-down Mode

Stand-by Mode

ABh

1 2 3 4 6 75

3 Dummy Bytes

Command

Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode)

Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode)

21 345670tRES1

Stand-by Mode

Deep Power-down Mode

High-Z

SCLK

CS#

ABh

Command

Mode 3

Mode 0

Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

ABh

0 1

RES1

Deep Power-down Mode Stand-by Mode

Command

Mode 3

Mode 0

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9-5. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID values

are listed in Table 6. ID Definitions.

The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed by two

dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Macronix (C2h) and the device

ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address byte is 00h, the

manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then the device ID will be

output first, followed by the manufacturer ID. While CS# is low, the manufacturer and device IDs can be read con-

tinuously, alternating from one to the other. The instruction is completed by driving CS# high.

Note: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

15 14 13 3 2 1 0

21 3456789 10

2 Dummy Bytes

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

Manufacturer ID

ADD (1)

MSB

76543210

Device ID

MSB MSB

765432 0

3531302928

SCLK

CS#

SCLK

CS#

90h

High-Z

Command

Mode 3

Mode 0

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Rev. 1.6, July 22, 2016P/N: PM1795

9-6. QPI ID Read (QPIID)

User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue

QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most significant

bit (MSB) first.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 6. ID Definitions

Command Type MX25L12835F

RDID 9Fh Manufacturer ID Memory type Memory density

C2 20 18

RES ABh Electronic ID

REMS 90h Manufacturer ID Device ID

C2 17

QPIID AFh Manufacturer ID Memory type Memory density

C2 20 18

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9-7. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even

in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data

out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 16. Read Status Register (RDSR) Sequence (SPI Mode)

21 3456789 10 11 12 13 14 15

command

76543210

Status Register Out

High-Z

MSB

76543210

Status Register Out

MSB

SCLK

CS#

05h

Mode 3

Mode 0

Figure 17. Read Status Register (RDSR) Sequence (QPI Mode)

0 1 3

SCLK

SIO[3:0]

CS#

05h

H0 L0

MSB LSB

4 5 7

H0 L0

H0 L0 H0 L0

Status ByteStatus ByteStatus ByteStatus Byte

Mode 3

Mode 0

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9-8. Read Configuration Register (RDCR)

The RDCR instruction is for reading Configuration Register Bits. The Read Configuration Register can be read at

any time (even in program/erase/write configuration register condition). It is recommended to check the Write in

Progress (WIP) bit before sending a new instruction when a program, erase, or write configuration register operation

is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configuration Reg-

ister data out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 18. Read Configuration Register (RDCR) Sequence (SPI Mode)

21 3456789 10 11 12 13 14 15

command

76543210

Configuration register Out

High-Z

MSB

76543210

Configuration register Out

MSB

SCLK

CS#

15h

Mode 3

Mode 0

Figure 19. Read Configuration Register (RDCR) Sequence (QPI Mode)

0 1 3

SCLK

SIO[3:0]

CS#

15h

H0 L0

MSB LSB

4 5 7

H0 L0

H0 L0 H0 L0

Mode 3

Mode 0

Config. ByteConfig. ByteConfig. ByteConfig. Byte

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WREN command

Program/erase command

Write program data/address

(Write erase address)

RDSR command

Read array data

(same address of PGM/ERS)

Program/erase successfully

Yes

Program/erase fail

start

Verify OK?

WIP=0?

Program/erase

another block?

Program/erase completed

Yes

RDSR command*

Yes

WEL=1? No

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Figure 20. Program/Erase flow with read array data

For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:

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Figure 21. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)

WREN command

Program/erase command

Write program data/address

(Write erase address)

RDSR command

RDSCUR command

Program/erase successfully

Yes

Program/erase fail

Yes

start

P_FAIL/E_FAIL =1 ?

WIP=0?

Program/erase

another block?

Program/erase completed

Yes

RDSR command*

Yes

WEL=1? No

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

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Status Register

Note 1: Please refer to the Table 2. Protected Area Sizes.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SRWD (status

protect)

(Quad

Enable)

BP3

(level of

protected

block)

BP2

(level of

protected

block)

BP1

(level of

protected

block)

BP0

(level of

protected

block)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=status

disabled

0=status

enabled

1=Quad

Enable

0=not Quad

Enable

(note 1) (note 1) (note 1) (note 1)

1=write

enable

0=not write

enable

1=write

operation

0=not in write

operation

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit

Non-volatile

bit volatile bit volatile bit

Status Register

The definition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta-

tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register

progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register

cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device

will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is ap-

plied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/

erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs

to be confirm to be 0.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area

(as defined in Table 2. Protected Area Sizes) of the device to against the program/erase instruction without hardware

protection mode being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR)

instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector

Erase (SE), Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits

(BP3:BP0) set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is un-

protected.

QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,

RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other

word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET# will be disabled.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

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Configuration Register

The Configuration Register is able to change the default status of Flash memory. Flash memory will be configured

after the CR bit is set.

ODS bit

The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as

defined in Output Driver Strength Table) of the device. The Output Driver Strength is defaulted as 30 Ohms when

delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to configure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

Table 7. Configuration Register Table

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

DC1

(Dummy

cycle 1)

DC0

(Dummy

cycle 0)

Reserved Reserved

(top/bottom

selected)

ODS 2

(output driver

strength)

ODS 1

(output driver

strength)

ODS 0

(output driver

strength)

(note 2) (note 2) x x

0=Top area

protect

1=Bottom

area protect

(Default=0)

(note 1) (note 1) (note 1)

volatile bit volatile bit x x OTP volatile bit volatile bit volatile bit

Note 1: Please refer to Output Driver Strength Table

Note 2: Please refer to Dummy Cycle and Frequency Table (MHz)

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Dummy Cycle and Frequency Table (MHz)

DC[1:0] Numbers of Dummy

clock cycles Fast Read Dual Output Fast

Read

Quad Output Fast

Read

00 (default) 8 104 104 104

01 6 104 104 84

10 8 104 104 104

11 10 133 133 133

Output Driver Strength Table

ODS2 ODS1 ODS0 Description Note

0 0 0 Reserved

Impedance at VCC/2

0 0 1 90 Ohms

0 1 0 60 Ohms

0 1 1 45 Ohms

1 0 0 Reserved

1 0 1 20 Ohms

1 1 0 15 Ohms

1 1 1 30 Ohms (Default)

DC[1:0] Numbers of Dummy

clock cycles Dual IO Fast Read

00 (default) 4 84

01 6 104

10 8 104

11 10 133

DC[1:0] Numbers of Dummy

clock cycles Quad IO Fast Read

00 (default) 6 84

01 4 70

10 8 104

11 10 133

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Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 22. Write Status Register (WRSR) Sequence (SPI Mode)

21 3456789 10 11 12 13 14 15

Status

Configuration

MSB

SCLK

CS#

01h

High-Z

command

Mode 3

Mode 0

16 17 18 19 20 21 22 23

765 4321 0 15 14 13 12 11 10 9 8

Figure 23. Write Status Register (WRSR) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

2 3 510 4

H0 L0 H1 L1

Command SR in CR in

Mode 3 Mode 3

Mode 0 Mode 0

01h

9-9. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,

BP0) bits to define the protected area of memory (as shown in Table 2. Protected Area Sizes). The WRSR also can

set or reset the Quad enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance

with Write Protection (WP#/SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register.

The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and

not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes

high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write En-

able Latch (WEL) bit is reset.

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 8. Protection Modes

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.

Protected Area Sizes.

Mode Status register condition WP# and SRWD bit status Memory

Software protection

mode (SPM)

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

bits can be changed

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

The SRWD, BP0-BP3 of

status register bits cannot be

changed

WP#=0, SRWD bit=1

The protected area

cannot

be program or erase.

Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,

BP0 and T/B bit, is at software protected mode (SPM).

- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values

of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0 and T/B bit, is at

software protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modification.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.

If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only

can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.

If the system enter QPI or set QE=1, the feature of HPM will be disabled.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 24. WRSR flow

WREN command

WRSR command

Write status register data

RDSR command

WRSR successfully

Yes

WRSR fail

start

Verify OK?

WIP=0? No

RDSR command

Yes

WEL=1? No

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 25. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

High-Z

01h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

tWHSL tSHWL

SCLK

CS#

WP#

Note: WP# must be kept high until the embedded operation finish.

MACRDNIX INTERVATIONAL Co., LTD.

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9-10. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address

is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been

reached.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on

SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 26. Read Data Bytes (READ) Sequence (SPI Mode only)

SCLK

CS#

21 3456789 10 28 29 30 31 32 33 34 35

22 21 3210

36 37 38

76543 1 7

Data Out 1

MSB

Data Out 2

03h

High-Z

command

Mode 3

Mode 0

24-Bit Address

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-11. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at

any location. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when

the highest address has been reached.

Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ

instruction code→ 3-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_READ opera-

tion can use CS# to high at any time during data out.

In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can

make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-

wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from

performance enhance mode and return to normal operation.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-

pact on the Program/Erase/Write Status Register current cycle.

Figure 27. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)

21 3456789 10 28 29 30 31

22 21 3210

High-Z

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Configurable

Dummy Cycle

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

SCLK

CS#

SCLK

CS#

0Bh

Command

Mode 3

Mode 0

24-Bit Address

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9-12. Dual Output Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruc-

tion, the following data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing DREAD instruction is: CS# goes low→ sending DREAD instruction→3-byte address on

SIO0→ 8 dummy cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→ to end DREAD operation can

use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 28. Dual Read Mode Sequence

High Impedance

21 3456780

SCLK

SI/SIO0

SO/SIO1

CS#

930 31 32 39 40 41 43 44 4542

3B D4

D6 D6 D4

D7 D5

Command 24 ADD Cycle Configurable

Dummy Cycle

A23 A22 A1 A0

… …

…

Data Out

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-13. 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-

mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next

higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-

tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-

tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 3-byte address inter-

leave on SIO1 & SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to end

2READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 29. 2 x I/O Read Mode Sequence (SPI Mode only)

21 3456780

SCLK

SI/SIO0

SO/SIO1

CS#

9 10 17 18 19 20

BBh

21 22 23 24 25 26 27 28 29 30

Command Configurable

Dummy Cycle

Mode 3

Mode 0

Mode 3

Mode 0

12 ADD Cycles

A23 A21 A19 A5 A3 A1

A4 A2 A0A22 A20 A18

D6 D4

D7 D5

Data

Out 1

Data

Out 2

D2 D0

D3 D1

D6 D4

D7 D5

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-14. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial Flash in read mode. The address is latched on rising edge

of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum

frequency fQ. The first address byte can be at any location. The address is automatically increased to the next high-

er address after each byte data is shifted out, so the whole memory can be read out at a single QREAD instruction.

The address counter rolls over to 0 when the highest address has been reached. Once writing QREAD instruction,

the following data out will perform as 4-bit instead of previous 1-bit.

The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte address on

SI → 8 dummy cycle (Default) → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD operation can

use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

High Impedance

21 3456780

SCLK

SIO0

SIO1

CS#

930 31 32 33 38 39 40 41 42

High Impedance

SIO2

High Impedance

SIO3

Configurable

dummy cycles

D4 D0

D5 D1

D6 D2

D7 D3

D4 D0

D5 D1

D6 D2

D7 D3

A23 A22 A2 A1 A0

Command 24 ADD Cycles Data

Out 1

Data

Out 2

Data

Out 3

…

Figure 30. Quad Read Mode Sequence

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-15. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg-

ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and

data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ.

The first address byte can be at any location. The address is automatically increased to the next higher address af-

ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following

address/dummy/data out will perform as 4-bit instead of previous 1-bit.

4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low→ sending

4READ instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out

interleave on SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to high at any time during data out.

4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence

of issuing 4READ instruction QPI mode is: CS# goes low→ sending 4READ instruction→ 3-byte address interleave

on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3, SIO2, SIO1 & SIO0→ to

end 4READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

MACRDNIX INTERVATIONAL Co., LTD. _\ D4 an as m D6 D2 07 m

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 31. 4 x I/O Read Mode Sequence (SPI Mode)

21 3456780

SCLK

SIO0

SIO1

SIO2

SIO3

CS#

9 1210 11 13 14

EBh

P4 P0

P5 P1

P6 P2

P7 P3

15 16 17 18 19 20 21 22

23 24

Command

Configurable

Dummy Cycle (Note 3)

Performance

enhance

indicator (Note 1)

Mode 3

Mode 0

6 ADD Cycles

A21 A17 A13 A9 A5 A1

A8 A4 A0A20 A16 A12

A23 A19 A15 A11 A7 A3

A10 A6 A2A22 A18 A14

D4 D0

D5 D1

Data

Out 1

Data

Out 2

Data

Out 3

D4 D0

D5 D1

D4 D0

D5 D1

D6 D2

D7 D3

D6 D2

D7 D3

D6 D2

D7 D3

Mode 3

Mode 0

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

3. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

configuration register.

Figure 32. 4 x I/O Read Mode Sequence (QPI Mode)

3 EDOM

SCLK

SIO[3:0]

CS#

MODE 3

A5 A4 A3 A2 A1 A0 X X

MODE 0MODE 0

MSB

Data Out

EB H0 L0 H1 L1 H2 L2 H3 L3

X X X X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Data In 24-bit Address Configurable

Dummy Cycle

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MX25L12835F

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The wrap around unit is defined within the 256Byte page, with random initial address. It is defined as “wrap-around

mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command

in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change

wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “EBh” and SPI “EBh”

support wrap around feature after wrap around is enabled. Burst read is supported in both SPI and QPI mode. The

device is default without Burst read.

CS#

SCLK

SIO

C0h D7 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 6 7 8 9 10 1112 13 14 155

Mode 3

Mode 0

Figure 33. SPI Mode

Figure 34. QPI Mode

CS#

SCLK

SIO[3:0]

MSB LSB

L0C0h

1 2 3

Mode 3

Mode 0

Note: MSB=Most Significant Bit

LSB=Least Significant Bit

9-16. Burst Read

This device supports Burst Read in both SPI and QPI mode.

To set the Burst length, following command operation is required to issue command: “C0h” in the first Byte (8-clocks),

following 4 clocks defining wrap around enable with “0h” and disable with“1h”.

The next 4 clocks are to define wrap around depth. Their definitions are as the following table:

Data Wrap Around Wrap Depth

00h Yes 8-byte

01h Yes 16-byte

02h Yes 32-byte

03h Yes 64-byte

1xh No X

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-17. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

Performance enhance mode is supported in both SPI and QPI mode.

In QPI mode, “EBh” and SPI “EBh” commands support enhance mode. The performance enhance mode is not

supported in dual I/O mode.

To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh

can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer

toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.

Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and

return to normal operation.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of

the first clock as address instead of command cycle.

This sequence of issuing 4READ instruction is especially useful in random access: CS# goes low→send 4READ

instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit P[7:0]→

4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (the following 4READ instruction is

ignored) → 3-bytes random access address.

To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle, 8 clocks, should be is-

sued in 1I/O sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in 4I/O should be issued.

If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.

MACRDNIX INTERVATIONAL Co., LTD. _ ‘ A9 M M m mmjmwwm _ M p, m mjm emu“

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 35. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)

21 3456780

SCLK

SIO0

SIO1

CS#

9 1210 11 13 14

EBh

15 16

n+1 ........... ...... ........... ...........n+7 n+9 n+13

17 18 19 20 21 22 n

SIO2

SIO3

SIO0

SIO1

SIO2

SIO3

Performance

enhance

indicator (Note 1)

SCLK

CS#

Performance

enhance

indicator (Note 1)

Mode 3

Mode 0

A21 A17 A13 A9 A5 A1

A8 A4 A0A20 A16 A12

A23 A19 A15 A11 A7 A3

A10 A6 A2A22 A18 A14

P4 P0

P5 P1

P6 P2

P7 P3

A21 A17 A13 A9 A5 A1

A8 A4 A0A20 A16 A12

A23 A19 A15 A11 A7 A3

A10 A6 A2A22 A18 A14

P4 P0

P5 P1

P6 P2

P7 P3

Command

Configurable

Dummy Cycle

(Note 2)

6 ADD Cycles

D4 D0

D5 D1

Data

Out 1

Data

Out 2

Data

Out n

D4 D0

D5 D1

D4 D0

D5 D1

D6 D2

D7 D3

D6 D2

D7 D3

D6 D2

D7 D3

D4 D0

D5 D1

Data

Out 1

Data

Out 2

Data

Out n

D4 D0

D5 D1

D4 D0

D5 D1

D6 D2

D7 D3

D6 D2

D7 D3

D6 D2

D7 D3

Mode 3

Mode 0

Configurable

Dummy Cycle

(Note 2)

Notes:

1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

2. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

configuration register.

MACRONI’X INTERVATIDNAL Co., LTD.

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Rev. 1.6, July 22, 2016P/N: PM1795

Figure 36. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

A5 A4 A3 A2 A1 A0

Data Out

Data In

EBh X

P(7:4) P(3:0)

X X X H0 L0 H1 L1

Configurable

Dummy Cycle (Note 1)

Configurable

Dummy Cycle (Note 1)

performance

enhance

indicator

SCLK

SIO[3:0]

CS#

A5 A4 A3 A2 A1 A0

Data Out

MSB LSB MSB LSB

P(7:4) P(3:0)

X X X H0 L0 H1 L1

performance

enhance

indicator

n+1 .............

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Mode 3

Mode 0

6 Address cycles

Notes:

1. Configuration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

configuration register.

2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

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Fast Boot Register (FBR)

Note: If FBSD = 11, the maximum clock frequency is 133 MHz

If FBSD = 10, the maximum clock frequency is 104 MHz

If FBSD = 01, the maximum clock frequency is 84 MHz

If FBSD = 00, the maximum clock frequency is 70 MHz

9-18. Fast Boot

The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset

without any read instruction.

A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also define the number of

delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and

ESFBR (erase fast boot register) can be used for the status configuration or alternation of the Fast Boot Register

bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default

number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.

When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).

After CS# returns to go high, the device will go back to standard SPI mode. In the fast boot data out process from

CS# goes low to CS# goes high, a minimum of one byte must be output.

Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,

reset command, or hardware reset operation.

The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data

is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.

Bits Description Bit Status Default State Type

31 to 4 FBSA (FastBoot Start

Address)

16 bytes boundary address for the start of boot

code access. FFFFFFF Non-

Volatile

3 x 1 Non-

Volatile

2 to 1 FBSD (FastBoot Start

Delay Cycle)

00: 7 delay cycles

01: 9 delay cycles

10: 11 delay cycles

11: 13 delay cycles

11 Non-

Volatile

0 FBE (FastBoot Enable) 0=FastBoot is enabled.

1=FastBoot is not enabled. 1Non-

Volatile

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Figure 37. Fast Boot Sequence (QE bit =0)

n+2

Delay Cycles

76543210

Data Out 1

High Impedance

MSB

76543210

Data Out 2

MSB

SCLK

CS#

Mode 3

Mode 0

------

nn+1 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10n+11n+12n+13n+14n+15

Don’t care or High Impedance

MSB

Figure 38. Fast Boot Sequence (QE bit =1)

5 1 5 1

4 4 4

000

5 1

-------n

High Impedance

6 2 6 2 6 2

7 3 7 3 7 3

6 2

7 3

SCLK

CS#

SIO0

SIO1

SIO3

SIO2

MSB

Delay Cycles

n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9

Mode 3

Mode 0

Data

Out 1

High Impedance

Data

Out 2

Data

Out 3

Data

Out 4

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

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Figure 39. Read Fast Boot Register (RDFBR) Sequence

21 34567890

SCLK

CS#

16h

Command

Mode 3 3710 38 39 40 41

Mode 0

MSB

7 6 7 65 25 2426

High-Z

MSB

Data Out 1 Data Out 2

Figure 40. Write Fast Boot Register (WRFBR) Sequence

21 34567890

MSB

SCLK

CS#

17h

Command

Mode 3 37 38 39

Mode 0

Fast Boot Register

High-Z

7 6 25 2426

Figure 41. Erase Fast Boot Register (ESFBR) Sequence

21 34567

High-Z

18h

Command

SCLK

CS#

Mode 3

Mode 0

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Figure 42. Sector Erase (SE) Sequence (SPI Mode)

21 3456789 29 30 310

A23 A22 A2 A1 A0

MSB

SCLK

CS#

20h

Command

Mode 3

Mode 0

24-Bit Address

Figure 43. Sector Erase (SE) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

20h

2 3 5 710

A5 A4

MSB

A3 A2

A1 A0

Command

Mode 3

Mode 0

24-Bit Address

9-19. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for

any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before

sending the Sector Erase (SE). Any address of the sector (see Table 4. Memory Organization) is a valid address

for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least significant bit of the

address byte been latched-in); otherwise, the instruction will be rejected and not executed.

Address bits [Am-A12] (Am is the most significant address) select the sector address.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→

CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Sector Erase (SE) instruction will not be executed on the block.

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9-20. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch

(WEL) bit before sending the Block Erase (BE32K). Any address of the block (see Table 4. Memory Organization) is

a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least

significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address

on SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the

tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If

the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Pro-

tect Mode), the Block Erase (BE32K) instruction will not be executed on the block.

Figure 44. Block Erase 32KB (BE32K) Sequence (SPI Mode)

21 3456789 29 30 310

MSB

SCLK

CS#

52h

Command

Mode 3

Mode 0

24-Bit Address

A23 A22 A2 A1 A0

Figure 45. Block Erase 32KB (BE32K) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

52h

2 3 5 710

A5 A4

MSB

A3 A2

A1 A0

Command

Mode 3

Mode 0

24-Bit Address

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9-21. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for

64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch

(WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to Table 4. Memory Organi-

zation) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the

least significant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→

CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE

timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block

is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),

the Block Erase (BE) instruction will not be executed on the block.

Figure 46. Block Erase (BE) Sequence (SPI Mode)

21 3456789 29 30 310

MSB

SCLK

CS#

D8h

Command

Mode 3

Mode 0

24-Bit Address

A23 A22 A2 A1 A0

Figure 47. Block Erase (BE) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

D8h

2 310

A5 A4

MSB

4 5

A3 A2

6 7

A1 A0

Command

Mode 3

Mode 0

24-Bit Address

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9-22. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-

tion must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must

go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE tim-

ing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase(CE) instruction will not be execut-

ed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

When the chip is under "Advances Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be ex-

ecuted on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected in

top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 48. Chip Erase (CE) Sequence (SPI Mode)

21 345670

60h or C7h

SCLK

CS#

Command

Mode 3

Mode 0

Figure 49. Chip Erase (CE) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

60h or C7h

0 1

Command

Mode 3

Mode 0

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9-23. Page Program (PP)

The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the de-

vice to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)

bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256

data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires

that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] specifies the starting

address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected

page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be pro-

grammed, A[7:0] should be set to 0.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at

least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte

boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex-

ecuted.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP

timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode) the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

A nnnnnn

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 50. Page Program (PP) Sequence (SPI Mode)

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 3456789 10 28 29 30 31 32 33 34 35

22 21 3210

36 37 38

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

SCLK

CS#

SCLK

CS#

02h

Command

Mode 3

Mode 0

24-Bit Address

Figure 51. Page Program (PP) Sequence (QPI Mode)

210

SCLK

SIO[3:0]

CS#

Data Byte

Data In

02h

A5 A4 A3 A2 A1 A0

H0 L0 H1 L1 H2 L2 H3 L3 H255 L255

Data Byte

256

......

Command

Mode 3

Mode 0

24-Bit Address

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9-24. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-

struction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" be-

fore sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and

SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.

The other function descriptions are as same as standard page program.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on

SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Pro-

tect Mode), the Quad Page Program (4PP) instruction will not be executed.

Figure 52. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

A20

A21 A17

A16 A12 A8 A4 A0

A13 A9 A5 A1

4 4 4 40 0 0 0

5 5 5 51 1 1 1

21 3456789

6 Address cycle Data

Byte 1

Data

Byte 2

Data

Byte 3

Data

Byte 4

A22 A18 A14 A10 A6 A2

A23 A19 A15 A11 A7 A3

6 6 6 62 2 2 2

7 7 7 73 3 3 3

SCLK

CS#

SIO0

SIO1

SIO3

SIO2

38h

Command

10 11 12 13 14 15 16 17 18 19 20 21

Mode 3

Mode 0

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9-25. Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby cur-

rent is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction

to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are

ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby

mode.

The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)

and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being

reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and

when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the

byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.

As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.

Figure 53. Deep Power-down (DP) Sequence (SPI Mode)

21 345670tDP

Deep Power-down Mode

Stand-by Mode

SCLK

CS#

B9h

Command

Mode 3

Mode 0

Figure 54. Deep Power-down (DP) Sequence (QPI Mode)

SCLK

SIO[3:0]

CS#

B9h

0 1

tDP

Deep Power-down Mode

Stand-by Mode

Command

Mode 3

Mode 0

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9-26. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured

OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array

and may be used to store unique serial number for system identifier. After entering the Secured OTP mode, follow

standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated

again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or pro-

gram procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

9-27. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-28. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register

data out on SO→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-29. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction

is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO

bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area

cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

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bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

WPSEL E_FAIL P_FAIL Reserved

ESB

(Erase

Suspend bit)

PSB

(Program

Suspend bit)

LDSO

(indicate if

lock-down)

Secured OTP

indicator bit

0=normal

WP mode

1=individual

mode

(default=0)

0=normal

Erase

succeed

1=indicate

Erase failed

(default=0)

0=normal

Program

succeed

1=indicate

Program

failed

(default=0)

0=Erase

is not

suspended

1= Erase

suspended

(default=0)

0=Program

is not

suspended

1= Program

suspended

(default=0)

0 = not lock-

down

1 = lock-down

(cannot

program/

erase

OTP)

0 = non-

factory

lock

1 = factory

lock

Non-volatile

bit (OTP) Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit

Non-volatile

bit

(OTP)

Non-volatile

bit (OTP)

Table 9. Security Register Definition

Security Register

The definition of the Security Register bits is as below:

Write Protection Selection bit. Please reference to Write Protection Selection

Erase Fail bit. The Erase Fail bit is a status flag, which shows the status of last Erase operation. It will be set to "1",

if the erase operation fails. It will be set to "0", if the last operation is success. Please note that it will not interrupt or

stop any operation in the flash memory.

Program Fail bit. The Program Fail bit is a status flag, which shows the status of last Program operation. It will be

set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is

success. Please note that it will not interrupt or stop any operation in the flash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use

ESB to identify the state of flash memory. After the flash memory is suspended by Erase Suspend command, ESB

is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may

use PSB to identify the state of flash memory. After the flash memory is suspended by Program Suspend command,

PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory or not. When it is

"0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-

tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP

area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.

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9-30. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Protection (BP) mode or (2) Advanced

Sector Protection mode. The protection modes are mutually exclusive. The WPSEL bit selects which protection

mode is enabled. If WPSEL=0 (factory default), BP mode is enabled and Advanced Sector Protection mode is disa-

bled. If WPSEL=1, Advanced Sector Protection mode is enabled and BP mode is disabled. The WPSEL command

is used to set WPSEL=1. A WREN command must be executed to set the WEL bit before sending the WPSEL com-

mand. Please note that the WPSEL bit is an OTP bit. Once WPSEL is set to “1”, it cannot be programmed

back to “0”.

When WPSEL = 0: Block Protection (BP) mode,

The memory array is write protected by the BP3~BP0 bits.

When WPSEL =1: Advanced Sector Protection mode,

Blocks are individually protected by their own SPB or DPB. On power-up, all blocks are write protected by the Dy-

namic Protection Bits (DPB) by default. The Advanced Sector Protection instructions WRLR, RDLR, WRPASS, RD-

PASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK, WRDPB, RDDPB, GBLK, and GBULK are activated. The

BP3~BP0 bits of the Status Register are disabled and have no effect. Hardware protection is performed by driving

WP#=0. Once WP#=0 all blocks and sectors are write protected regardless of the state of each SPB or DPB.

The sequence of issuing WPSEL instruction is: CS# goes low → send WPSEL instruction to enable the Advanced

Sector Protect mode → CS# goes high.

Write Protection Selection

Start

(Default in BP Mode)

Set

WPSEL Bit

WPSEL=0WPSEL=1

Bit 2 =0

Bit 1 =0

Block Protection

(BP)

Advance

Sector Protection

Set

Lock Register

Password

Protection

Solid

Protection

Dynamic

Protection

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Figure 55. WPSEL Flow

RDSCUR command

RDSR command

RDSCUR command

WPSEL set successfully

Yes

WPSEL set fail

start

WPSEL=1?

WIP=0? No

WPSEL disable,

block protected by BP[3:0]

Yes

WREN command

WPSEL=1?

WPSEL command

WPSEL enable.

Block protected by Advance Sector Protection

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9-31. Advanced Sector Protection

Advanced Sector Protection can protect individual 4KB sectors in the bottom and top 64KB of memory and protect

individual 64KB blocks in the rest of memory.

There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB) assigned to each

4KB sector at the bottom and top 64KB of memory and to each 64KB block in the rest of memory. A sector or block

is write-protected from programming or erasing when its associated SPB or DPB is set to “1”. The Unprotect Solid

Protect Bit (USPB) can temporarily override and disable the write-protection provided by the SPB bits.

There are two mutually exclusive implementations of Advanced Sector Protection: Solid Protection mode (factory

default) and Password Protection mode. Solid Protection mode permits the SPB bits to be modified after power-on

or a reset. The Password Protection mode requires a valid password before allowing the SPB bits to be modified.

The figure below is an overview of Advanced Sector Protection.

Figure 56. Advanced Sector Protection Overview

Start

Bit 1=0 Bit 2=0

Password Protection Mode

Set

Lock Register ?

Set

SPB Lock Bit ?

SPBLK = 0

SPBLK = 1

SPB Lock bit Unlocked

SPB is changeable

SPB Access Register

(SPB)

Dynamic Protect Bit Register

(DPB)

SPB=1 Write Protect

SPB=0 Write Unprotect

SPB 0

SPB 1

SPB 2

SPB N-1

SPB N

SA 0

SA 1

SA 2

SA N-1

SA N

DPB 0

DPB 1

DPB 2

DPB N-1

DPB N

SPB Lock bit locked

All SPB can not be changeable

Solid Protection Mode

Set 64 bit Password

Sector Array

DPB=1 sector protect

DPB=0 sector unprotect

Temporary Unprotect

SPB bit (USPB)

USPB=0 SPB bit is disabled

USPB=1 SPB bit is effective

USPB

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9-31-1. Lock Register

The Lock Register is a 16-bit one-time programmable register. Lock Register bits [2:1] select between Solid

Protection mode and Password Protection mode. When both bits are “1” (factory default), Solid Protection mode

is enabled by default. The Lock Register is programmed using the WRLR (Write Lock Register) command.

Programming Lock Register bit 1 to “0” permanently selects Solid Protection mode and permanently disables

Password Protection mode. Conversely, programming bit 2 to “0” permanently selects Password Protection mode

and permanently disables Solid Protection mode. Bits 1 and 2 cannot be programmed to “0” at the same time

otherwise the device will abort the operation. A WREN command must be executed to set the WEL bit before

sending the WRLR command.

A password must be set prior to selecting Password Protection mode. The password can be set by issuing the

WRPASS command.

Lock Register

Bit 15-3 Bit 2 Bit 1 Bit0

Reserved Password Protection Mode Lock Bit Solid Protection Mode Lock Bit Reserved

0=Password Protection Mode Enable

1= Password Protection Mode not

enable (Default =1)

0=Solid Protection Mode Enable

1= Solid Protection Mode not enable (Default =1) x

OTP OTP OTP OTP

Figure 57. Read Lock Register (RDLR) Sequence

21 3456789 10 11 12 13 14 15

command

76543210

High-Z

MSB

15 14 13 12 11 10 9 8

MSB

SCLK

CS#

2Dh

Mode 3

Mode 0

Figure 58. Write Lock Register (WRLR) Sequence (SPI Mode)

21 3456789 10 11 12 13 14 15

Lock Register In

MSB

SCLK

CS#

2Ch

High-Z

Command

Mode 3

Mode 0

16 17 18 19 20 21 22 23

765 4321 0 15 14 13 12 11 10 9 8

Note: Once bit 2 or bit 1 has been programmed to "0", the other bit can't be changed any more. Attempts to clear

more than one bit in the Lock Register will set the Security Register P_FAIL flag to "1".

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-31-2. SPB Lock Bit (SPBLK)

The SPB Lock Bit (SPBLK) is a volatile bit located in bit 0 of the SPB Lock Register. The SPBLK bit controls whether

the SPB bits can be modified or not. If SPBLK=1, the SPB bits are unprotected and can be modified. If SPBLK=0,

the SPB bits are protected (“locked”) and cannot be modified. The power-on and reset status of the SPBLK bit is

determined by Lock Register bits [2:1]. Refer to SPB Lock Register for SPBLK bit default power-on status. The

RDSPBLK command can be used to read the SPB Lock Register to determine the state of the SPBLK bit.

In Solid Protection mode, the SPBLK bit defaults to “1” after power-on or reset. When SPBLK=1, the SPB bits are

unprotected (“unlocked”) and can be modified. The SPB Lock Bit Set command can be used to write the SPBLK bit to “0”

and protect the SPB bits. A WREN command must be executed to set the WEL bit before sending the SPB Lock Bit

Set command. Once the SPBLK has been written to “0”, there is no command (except a software reset) to set the

bit back to “1”. A power-on cycle or reset is required to set the SPB lock bit back to “1”.

In Password Protection mode, the SPBLK bit defaults to “0” after power-on or reset. A valid password must

be provided to set the SPBLK bit to “1” to allow the SPBs to be modified. After the SPBs have been set to the

desired status, use the SPB Lock Bit Set command to clear the SPBLK bit back to “0” in order to prevent further

modification.

SPB Lock Register

Figure 59. SPB Lock Bit Set (SPBLK) Sequence

21 34567

High-Z

A6h

Command

SCLK

CS#

Mode 3

Mode 0

Figure 60. Read SPB Lock Register (RDSPBLK) Sequence

21 3456789 10 11 12 13 14 15

command

76543210

High-Z

MSB

76543210

MSB

SCLK

CS#

A7h

Mode 3

Mode 0

Bit Description Bit Status Default Type

7-1 Reserved X 0000000 Volatile

0SPBLK (SPB Lock Bit) 0 = SPBs protected

1= SPBs unprotected

Solid Protection Mode: 1

Password Protection Mode: 0 Volatile

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Rev. 1.6, July 22, 2016P/N: PM1795

9-31-3. Solid Protection Bits

The Solid Protection Bits (SPBs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks.

The SPB bits have the same endurance as the Flash memory. An SPB is assigned to each 4KB sector in the bottom

and top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of the SPB bits is “0”,

which has the sector/block write-protection disabled.

When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase operations on the

sector or block will be inhibited. SPBs can be individually set to “1” by the WRSPB command. However, the SPBs

cannot be individually cleared to “0”. Issuing the ESSPB command clears all SPBs to “0”. A WREN command must

be executed to set the WEL bit before sending the WRSPB or ESSPB command.

The SPBLK bit must be “1” before any SPB can be modified. In Solid Protection mode the SPBLK bit defaults to

“1” after power-on or reset. Under Password Protection mode, the SPBLK bit defaults to “0” after power-on or reset,

and a PASSULK command with a correct password is required to set the SPBLK bit to “1”.

The SPB Lock Bit Set command clears the SPBLK bit to “0”, locking the SPB bits from further modification.

The RDSPB command reads the status of the SPB of a sector or block. The RDSPB command returns 00h if the

SPB is “0”, indicating write-protection is disabled. The RDSPB command returns FFh if the SPB is “1”, indicating

write-protection is enabled.

In Solid Protection mode, the Unprotect Solid Protect Bit (USPB) can temporarily mask the SPB bits and disable the

write-protection provided by the SPB bits.

Note: If SPBLK=0, commands to set or clear the SPB bits will be ignored.

SPB Register

Bit Description Bit Status Default Type

7 to 0 SPB (Solid Protection Bit) 00h = Unprotect Sector / Block

FFh = Protect Sector / Block 00h Non-volatile

A nnnnnn

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 61. Read SPB Status (RDSPB) Sequence

21 34567890

MSB

SCLK

CS#

E2h

Command

Mode 3 37 38 39 40 41 42

Mode 0

32-Bit Address

(Note)

A31 A30 A2 A1 A0

76543210

High-Z

MSB

Data Out

43 44 45 46 47

Figure 62. SPB Erase (ESSPB) Sequence

21 34567

High-Z

E4h

Command

SCLK

CS#

Mode 3

Mode 0

Figure 63. SPB Program (WRSPB) Sequence

21 34567890

MSB

SCLK

CS#

E3h

Command

Mode 3 37 38 39

Mode 0

32-Bit Address

(Note)

A31 A30 A2 A1 A0

Note: A31-A24 are don't care.

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Rev. 1.6, July 22, 2016P/N: PM1795

9-31-4. Dynamic Protection Bits

The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enabling or disabling write-protection

to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to each

64KB block in the rest of the memory. The DBPs can enable write-protection on a sector or block regardless of the

state of the corresponding SPB. However, the DPB bits can only unprotect sectors or blocks whose SPB bits are “0”

(unprotected).

When a DPB is “1”, the associated sector or block will be write-protected, preventing any program or erase

operation on the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”, the

associated sector or block will be unprotected if the corresponding SPB is also “0”.

DPB bits can be individually set to “1” or “0” by the WRDPB command. The DBP bits can also be globally cleared to

“0” with the GBULK command or globally set to “1” with the GBLK command. A WREN command must be executed

to set the WEL bit before sending the WRDPB, GBULK, or GBLK command.

The RDDPB command reads the status of the DPB of a sector or block. The RDDPB command returns 00h if the

DPB is “0”, indicating write-protection is disabled. The RDDPB command returns FFh if the DPB is “1”, indicating

write-protection is enabled.

DPB Register

Figure 64. Read DPB Register (RDDPB) Sequence

21 34567890

MSB

SCLK

CS#

E0h

Command

Mode 3 37 38 39 40 41 42

Mode 0

32-Bit Address

(Note)

A31 A30 A2 A1 A0

76543210

High-Z

MSB

Data Out

43 44 45 46 47

Figure 65. Write DPB Register (WRDPB) Sequence

21 34567890

MSB

SCLK

CS#

E1h

Command

Mode 3 37 38 39 40 41 42

Mode 0

32-Bit Address

(Note)

A31 A30 A2 A1 A0

76543210

MSB

Data Byte 1

43 44 45 46 47

Note: A31-A24 are don't care.

Bit Description Bit Status Default Type

7 to 0 DPB (Dynamic Protection Bit) 00h = Unprotect Sector / Block

FFh = Protect Sector / Block FFh Volatile

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Rev. 1.6, July 22, 2016P/N: PM1795

9-31-5. Unprotect Solid Protect Bit (USPB)

The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or reset. When USPB=1, the SPBs

have their normal function. When USPB=0 all SPBs are masked and their write-protected sectors and blocks are

temporarily unprotected (as long as their corresponding DPBs are “0“). The USPB provides a means to temporarily

override the SPBs without having to issue the ESSPB and WRSPB commands to clear and set the SPBs. The

USPB can be set or cleared as often as needed.

Please refer to 9-31-7. Sector Protection States Summary Table for the sector state with the protection status of

DPB/SPB/USPB bits.

9-31-6. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective if WPSEL=1. The GBLK and GBULK instructions provide a quick method to set

or clear all DPB bits at once.

The WREN (Write Enable) instruction is required before issuing the GBLK/GBULK instruction.

The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction

→CS# goes high.

The GBLK and GBULK commands are accepted in both SPI and QPI mode.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

9-31-7. Sector Protection States Summary Table

Protection Status Sector/Block

Protection State

DPB SPB USPB

0 0 0 Unprotected

0 0 1 Unprotected

0 1 0 Unprotected

0 1 1 Protected

1 0 0 Protected

1 0 1 Protected

1 1 0 Protected

1 1 1 Protected

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-32. Password Protection Mode

Password Protection mode potentially provides a higher level of security than Solid Protection mode. In Password

Protection mode, the SPBLK bit defaults to “0” after a power-on cycle or reset. When SPBLK=0, the SPBs are

locked and cannot be modified. A 64-bit password must be provided to unlock the SPBs.

The PASSULK command with the correct password will set the SPBLK bit to “1” and unlock the SPB bits. After the

correct password is given, a wait of 2us is necessary for the SPB bits to unlock. The Status Register WIP bit will

clear to “0” upon completion of the PASSULK command. Once unlocked, the SPB bits can be modified. A WREN

command must be executed to set the WEL bit before sending the PASSULK command.

Several steps are required to place the device in Password Protection mode. Prior to entering the Password

Protection mode, it is necessary to set the 64-bit password and verify it. The WRPASS command writes the

password and the RDPASS command reads back the password. Password verification is permitted until the

Password Protection Mode Lock Bit has been written to “0”. Password Protection mode is activated by programming

the Password Protection Mode Lock Bit to “0”. This operation is not reversible. Once the bit is programmed, it

cannot be erased. The device remains permanently in Password Protection mode and the 64-bit password can

neither be retrieved nor reprogrammed..

The password is all “1’s” when shipped from the factory. The WRPASS command can only program password bits to “0”.

The WRPASS command cannot program “0’s” back to “1’s”. All 64-bit password combinations are valid password

options. A WREN command must be executed to set the WEL bit before sending the WRPASS command.

● The unlock operation will fail if the password provided by the PASSULK command does not match the stored

password. This will set the P_FAIL bit to “1” and insert a 100us ± 20us delay before clearing the WIP bit to “0”.

● The PASSULK command is prohibited from being executed faster than once every 100us ± 20us. This restriction

makes it impractical to attempt all combinations of a 64-bit password (such an effort would take ~58 million

years). Monitor the WIP bit to determine whether the device has completed the PASSULK command.

● When a valid password is provided, the PASSULK command does not insert the 100us delay before returning

the WIP bit to zero. The SPBLK bit will set to “1” and the P_FAIL bit will be “0”.

● It is not possible to set the SPBLK bit to “1” if the password had not been set prior to the Password Protection

mode being selected.

Password Register (PASS)

Bits Field

Name Function Type Default State Description

63 to 0 PWD Hidden

Password OTP FFFFFFFFFFFFFFFFh

Non-volatile OTP storage of 64 bit password. The

password is no longer readable after the Password

Protection mode is selected by programming Lock

MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 66. Read Password Register (RDPASS) Sequence

21 34567890

SCLK

CS#

27h

Command

Mode 3 69 70 71 72 73

Mode 0

MSB

7 6 7 657 5658

High-Z

MSB

Data Out 1 Data Out 2

Figure 67. Write Password Register (WRPASS) Sequence

21 34567890

MSB

SCLK

CS#

28h

Command

Mode 3 69 70 71

Mode 0

Password

7 6 58 57 56

High-Z

Figure 68. Password Unlock (PASSULK) Sequence

21 34567890

MSB

SCLK

CS#

29h

High-Z

Command

Mode 3 69 70 71

Mode 0

Password

7 6 58 57 56

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-33. Program/Erase Suspend/Resume

The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other

operations.

After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode

through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to Table 9. Security Register Definition)

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-34. Erase Suspend

Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode,

the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation.

Reading the sector or Block being erase suspended is invalid.

After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including:

03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h,

00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h)

If the system issues an Erase Suspend command after the sector erase operation has already begun, the device

will not enter Erase-Suspended mode until tESL time has elapsed.

Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state

of flash memory. After the flash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is

cleared to "0" after erase operation resumes.

9-35. Program Suspend

Program suspend allows the interruption of all program operations. After the device has entered Program-

Suspended mode, the system can read any sector(s) or Block(s) except those be ing programmed by the suspended

program operation. Reading the sector or Block being program suspended is invalid.

After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.

(including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h,

66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h)

Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the

state of flash memory. After the flash memory is suspended by Program Suspend command, PSB is set to "1". PSB

is cleared to "0" after program operation resumes.

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Figure 69. Suspend to Read Latency

CS#

tPSL / tESL

tPSL: Program Latency

tESL: Erase Latency

Suspend Command Read Command

Figure 70. Resume to Read Latency

CS#

tSE / tBE / tPP

Resume Command Read Command

Figure 71. Resume to Suspend Latency

CS#

tPRS / tERS

Resume Command Suspend Command

tPRS: Program Resume to another Suspend

tERS: Erase Resume to another Suspend

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Rev. 1.6, July 22, 2016P/N: PM1795

9-36. Write-Resume

The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in

Status register will be changed back to “0”.

The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive

CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed

or not. The user may also wait the time lag of tSE, tBE, tPP for Sector-erase, Block-erase or Page-programming.

WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires

latency time of 1ms.

Please note that, if "performance enhance mode" is executed during suspend operation, the device can not

be resumed. To restart the write command, disable the "performance enhance mode" is required. After the

"performance enhance mode" is disabled, the write-resume command is effective.

9-37. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any

other command.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

during SPI mode.

9-38. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)

command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which

makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform the

Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will

be invalid.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under

processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to Table 14. Reset Timing-

(Other Operation) for tREADY2.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 72. Software Reset Recovery

CS#

Mode

66 99

tREADY2

Stand-by Mode

Figure 73. Reset Sequence (SPI mode)

CS#

SCLK

SIO0 66h

Mode 3

Mode 0

Mode 3

Mode 0

99h

Command Command

tSHSL

Figure 74. Reset Sequence (QPI mode)

MODE 3

SCLK

SIO[3:0]

CS#

MODE 3

99h66h

MODE 0

MODE 3

MODE 0MODE 0

Command Command

tSHSL

Note: Refer to Table 14. Reset Timing-(Other Operation) for tREADY2.

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

9-39. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address

bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#

to high at any time during data out.

SFDP is a JEDEC Standard, JESD216.

Figure 75. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

21 3456789 10 28 29 30 31

22 21 3210

High-Z

24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Cycle

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

SCLK

CS#

SCLK

CS#

5Ah

Command

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 10. Signature and Parameter Identification Data Values

Description Comment Add (h)

(Byte)

DW Add

(Bit)

Data (h/b)

(Note1)

Data

(h)

SFDP Signature Fixed: 50444653h

00h 07:00 53h 53h

01h 15:08 46h 46h

02h 23:16 44h 44h

03h 31:24 50h 50h

SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h

SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h

Number of Parameter Headers This number is 0-based. Therefore,

0 indicates 1 parameter header. 06h 23:16 01h 01h

Unused 07h 31:24 FFh FFh

ID number (JEDEC) 00h: it indicates a JEDEC specified

header. 08h 07:00 00h 00h

Parameter Table Minor Revision

Number Start from 00h 09h 15:08 00h 00h

Parameter Table Major Revision

Number Start from 01h 0Ah 23:16 01h 01h

Parameter Table Length

(in double word)

How many DWORDs in the

Parameter table 0Bh 31:24 09h 09h

Parameter Table Pointer (PTP) First address of JEDEC Flash

Parameter table

0Ch 07:00 30h 30h

0Dh 15:08 00h 00h

0Eh 23:16 00h 00h

Unused 0Fh 31:24 FFh FFh

ID number

(Macronix manufacturer ID)

it indicates Macronix manufacturer

ID 10h 07:00 C2h C2h

Parameter Table Minor Revision

Number Start from 00h 11h 15:08 00h 00h

Parameter Table Major Revision

Number Start from 01h 12h 23:16 01h 01h

Parameter Table Length

(in double word)

How many DWORDs in the

Parameter table 13h 31:24 04h 04h

Parameter Table Pointer (PTP) First address of Macronix Flash

Parameter table

14h 07:00 60h 60h

15h 15:08 00h 00h

16h 23:16 00h 00h

Unused 17h 31:24 FFh FFh

SFDP Table below is for MX25L12835FM2I-10G, MX25L12835FMI-10G, MX25L12835FZ2I-10G and

MX25L12835FZNI-10G

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Table 11. Parameter Table (0): JEDEC Flash Parameter Tables

Description Comment Add (h)

(Byte)

DW Add

(Bit)

Data (h/b)

(Note1)

Data

(h)

Block/Sector Erase sizes

00: Reserved, 01: 4KB erase,

10: Reserved,

11: not support 4KB erase

30h

01:00 01b

E5h

Write Granularity 0: 1Byte, 1: 64Byte or larger 02 1b

Write Enable Instruction Required

for Writing to Volatile Status

Registers

0: not required

1: required 00h to be written to the

status register

03 0b

Write Enable Opcode Select for

Writing to Volatile Status Registers

0: use 50h opcode,

1: use 06h opcode

Note: If target flash status register is

nonvolatile, then bits 3 and 4 must

be set to 00b.

04 0b

Unused Contains 111b and can never be

changed 07:05 111b

4KB Erase Opcode 31h 15:08 20h 20h

(1-1-2) Fast Read (Note2) 0=not support 1=support

32h

16 1b

F1h

Address Bytes Number used in

addressing flash array

00: 3Byte only, 01: 3 or 4Byte,

10: 4Byte only, 11: Reserved 18:17 00b

Double Transfer Rate (DTR)

Clocking 0=not support 1=support 19 0b

(1-2-2) Fast Read 0=not support 1=support 20 1b

(1-4-4) Fast Read 0=not support 1=support 21 1b

(1-1-4) Fast Read 0=not support 1=support 22 1b

Unused 23 1b

Unused 33h 31:24 FFh FFh

Flash Memory Density 37h:34h 31:00 07FF FFFFh

(1-4-4) Fast Read Number of Wait

states (Note3)

0 0000b: Wait states (Dummy

Clocks) not support 38h

04:00 0 0100b

44h

(1-4-4) Fast Read Number of

Mode Bits (Note4) 000b: Mode Bits not support 07:05 010b

(1-4-4) Fast Read Opcode 39h 15:08 EBh EBh

(1-1-4) Fast Read Number of Wait

states

0 0000b: Wait states (Dummy

Clocks) not support 3Ah

20:16 0 1000b

08h

(1-1-4) Fast Read Number of

Mode Bits 000b: Mode Bits not support 23:21 000b

(1-1-4) Fast Read Opcode 3Bh 31:24 6Bh 6Bh

SFDP Table below is for MX25L12835FM2I-10G, MX25L12835FMI-10G, MX25L12835FZ2I-10G and

MX25L12835FZNI-10G

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MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Description Comment Add (h)

(Byte)

DW Add

(Bit)

Data (h/b)

(Note1)

Data

(h)

(1-1-2) Fast Read Number of Wait

states

0 0000b: Wait states (Dummy

Clocks) not support 3Ch

04:00 0 1000b

08h

(1-1-2) Fast Read Number of

Mode Bits 000b: Mode Bits not support 07:05 000b

(1-1-2) Fast Read Opcode 3Dh 15:08 3Bh 3Bh

(1-2-2) Fast Read Number of Wait

states

0 0000b: Wait states (Dummy

Clocks) not support 3Eh

20:16 0 0100b

04h

(1-2-2) Fast Read Number of

Mode Bits 000b: Mode Bits not support 23:21 000b

(1-2-2) Fast Read Opcode 3Fh 31:24 BBh BBh

(2-2-2) Fast Read 0=not support 1=support

40h

00 0b

FEh

Unused 03:01 111b

(4-4-4) Fast Read 0=not support 1=support 04 1b

Unused 07:05 111b

Unused 43h:41h 31:08 FFh FFh

Unused 45h:44h 15:00 FFh FFh

(2-2-2) Fast Read Number of Wait

states

0 0000b: Wait states (Dummy

Clocks) not support 46h

20:16 0 0000b

00h

(2-2-2) Fast Read Number of

Mode Bits 000b: Mode Bits not support 23:21 000b

(2-2-2) Fast Read Opcode 47h 31:24 FFh FFh

Unused 49h:48h 15:00 FFh FFh

(4-4-4) Fast Read Number of Wait

states

0 0000b: Wait states (Dummy

Clocks) not support 4Ah

20:16 0 0100b

44h

(4-4-4) Fast Read Number of

Mode Bits 000b: Mode Bits not support 23:21 010b

(4-4-4) Fast Read Opcode 4Bh 31:24 EBh EBh

Sector Type 1 Size Sector/block size = 2^N bytes (Note5)

0x00b: this sector type doesn't exist 4Ch 07:00 0Ch 0Ch

Sector Type 1 erase Opcode 4Dh 15:08 20h 20h

Sector Type 2 Size Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist 4Eh 23:16 0Fh 0Fh

Sector Type 2 erase Opcode 4Fh 31:24 52h 52h

Sector Type 3 Size Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist 50h 07:00 10h 10h

Sector Type 3 erase Opcode 51h 15:08 D8h D8h

Sector Type 4 Size Sector/block size = 2^N bytes

0x00b: this sector type doesn't exist 52h 23:16 00h 00h

Sector Type 4 erase Opcode 53h 31:24 FFh FFh

SFDP Table below is for MX25L12835FM2I-10G, MX25L12835FMI-10G, MX25L12835FZ2I-10G and

MX25L12835FZNI-10G

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 12. Parameter Table (1): Macronix Flash Parameter Tables

Description Comment Add (h)

(Byte)

DW Add

(Bit)

Data (h/b)

(Note1)

Data

(h)

Vcc Supply Maximum Voltage

2000h=2.000V

2700h=2.700V

3600h=3.600V

61h:60h 07:00

15:08

00h

36h

00h

36h

Vcc Supply Minimum Voltage

1750h=1.750V

1650h=1.650V

2250h=2.250V

2350h=2.350V

2700h=2.700V

63h:62h 23:16

31:24

00h

27h

00h

27h

H/W Reset# pin 0=not support 1=support

65h:64h

00 1b

F99Dh

H/W Hold# pin 0=not support 1=support 01 0b

Deep Power Down Mode 0=not support 1=support 02 1b

S/W Reset 0=not support 1=support 03 1b

S/W Reset Opcode Reset Enable (66h) should be

issued before Reset Opcode 11:04 1001 1001b

(99h)

Program Suspend/Resume 0=not support 1=support 12 1b

Erase Suspend/Resume 0=not support 1=support 13 1b

Unused 14 1b

Wrap-Around Read mode 0=not support 1=support 15 1b

Wrap-Around Read mode Opcode 66h 23:16 C0h C0h

Wrap-Around Read data length

08h:support 8B wrap-around read

16h:8B&16B

32h:8B&16B&32B

64h:8B&16B&32B&64B

67h 31:24 64h 64h

Individual block lock 0=not support 1=support

6Bh:68h

00 1b

CB85h

Individual block lock bit

(Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 0b

Individual block lock Opcode 09:02 1110 0001b

(E1h)

Individual block lock Volatile

protect bit default protect status 0=protect 1=unprotect 10 0b

Secured OTP 0=not support 1=support 11 1b

Read Lock 0=not support 1=support 12 0b

Permanent Lock 0=not support 1=support 13 0b

Unused 15:14 11b

Unused 31:16 FFh FFh

Unused 6Fh:6Ch 31:00 FFh FFh

MX25L12835FM2I-10G-SFDP_2014-09-24

SFDP Table below is for MX25L12835FM2I-10G, MX25L12835FMI-10G, MX25L12835FZ2I-10G and

MX25L12835FZNI-10G

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),

address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),

and (4-4-4)

Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.

Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller

if they are specified. (eg,read performance enhance toggling bits)

Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h

Note 6: All unused and undefined area data is blank FFh for SFDP Tables that are defined in Parameter

Identification Header. All other areas beyond defined SFDP Table are reserved by Macronix.

MACRDNIX INTERVATIONAL Co., LTD. If

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Symbol Parameter Min. Typ. Max. Unit

tRHSL Reset# high before CS# low 10 us

tRS Reset# setup time 15 ns

tRH Reset# hold time 15 ns

tRLRH Reset# low pulse width 10 us

tREADY1 Reset Recovery time 35 us

10. RESET

Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at

the following states:

- Standby mode

- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

- 3-byte address mode

If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data

could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to

minimum.

Figure 76. RESET Timing

tRHSL

tRS

tRH

tRLRH

tREADY1 / tREADY2

SCLK

RESET#

CS#

Table 13. Reset Timing-(Power On)

Symbol Parameter Min. Typ. Max. Unit

tRHSL Reset# high before CS# low 10 us

tRS Reset# setup time 15 ns

tRH Reset# hold time 15 ns

tRLRH Reset# low pulse width 10 us

tREADY2

Reset Recovery time (During instruction decoding) 40 us

Reset Recovery time (for read operation) 35 us

Reset Recovery time (for program operation) 310 us

Reset Recovery time(for SE4KB operation) 12 ms

Reset Recovery time (for BE64K/BE32KB operation) 25 ms

Reset Recovery time (for Chip Erase operation) 100 ms

Reset Recovery time (for WRSR operation) 40 ms

Table 14. Reset Timing-(Other Operation)

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

11. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct

level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and

the flash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The read, write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

Please refer to the Figure 83. Power-up Timing.

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-

ed. (generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response

to any command. The data corruption might occur during the stage while a write, program, erase cycle is in

progress.

MEI—II: MACRDNIX INTERVATIONAL Co., LTD. ans

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

12. ELECTRICAL SPECIFICATIONS

Figure 77. Maximum Negative Overshoot Waveform Figure 78. Maximum Positive Overshoot Waveform

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Specifications contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see

Figure 77 and Figure 78.

Table 15. ABSOLUTE MAXIMUM RATINGS

RATING VALUE

Ambient Operating Temperature Industrial grade -40°C to 85°C

Storage Temperature -65°C to 150°C

Applied Input Voltage -0.5V to VCC+0.5V

Applied Output Voltage -0.5V to VCC+0.5V

VCC to Ground Potential -0.5V to 4.0V

Table 16. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter Min. Typ. Max. Unit Conditions

CIN Input Capacitance 6 pF VIN = 0V

COUT Output Capacitance 8 pF VOUT = 0V

Vss

Vss-2.0V

20ns 20ns

20ns

Vcc + 2.0V

Vcc

20ns 20ns

20ns

MEI—II: MACRDNIX INTERVATIONAL Co., LTD. mgu

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 79. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Figure 80. OUTPUT LOADING

Measurement

Level

Input timing reference level Output timing reference level

0.8VCC 0.7VCC

0.8V

0.5VCC

0.2VCC

Note: Input pulse rise and fall time are <5ns

DEVICE UNDER

TEST

CL 25K ohm

25K ohm

+3.0V

CL=30pF Including jig capacitance

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 17. DC CHARACTERISTICS

Notes :

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

Symbol Parameter Notes Min. Typ. Max. Units Test Conditions

ILI Input Load Current 1 ±2 uA VCC = VCC Max,

VIN = VCC or GND

ILO Output Leakage Current 1 ±2 uA VCC = VCC Max,

VOUT = VCC or GND

ISB1 VCC Standby Current 1 10 50 uA VIN = VCC or GND,

CS# = VCC

ISB2 Deep Power-down

Current 2 20 uA VIN = VCC or GND,

CS# = VCC

ICC1 VCC Read 1 14

25 mA

f=133MHz, (4 x I/O read)

SCLK=0.1VCC/0.9VCC,

SO=Open

20 mA

f=104MHz, (4 x I/O read)

SCLK=0.1VCC/0.9VCC,

SO=Open

15 mA

f=84MHz,

SCLK=0.1VCC/0.9VCC,

SO=Open

ICC2 VCC Program Current

(PP) 1 14 20 mA Program in Progress,

CS# = VCC

ICC3 VCC Write Status

progress, CS#=VCC

ICC4

VCC Sector/Block (32K,

64K) Erase Current

(SE/BE/BE32K)

1 14 25 mA Erase in Progress,

CS#=VCC

ICC5 VCC Chip Erase Current

(CE) 1 14 25 mA Erase in Progress,

CS#=VCC

VIL Input Low Voltage -0.5 0.8 V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage 0.2 VIOL = 100uA

VOH Output High Voltage VCC-0.2 V IOH = -100uA

(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Table 18. AC CHARACTERISTICS

Symbol Alt. Parameter Min. Typ. Max. Unit

fSCLK fC Clock Frequency for all commands (except Read) D.C. 133 MHz

fRSCLK fR Clock Frequency for READ instructions 50 MHz

fTSCLK fT Clock Frequency for 2READ instructions 84(7) MHz

fQ Clock Frequency for 4READ instructions 84(7) MHz

tCH(1) tCLH Clock High Time Others (fSCLK) 3.3 ns

Normal Read (fRSCLK) 7 ns

tCL(1) tCLL Clock Low Time Others (fSCLK) 3.3 ns

Normal Read (fRSCLK) 7 ns

tCLCH(2) Clock Rise Time (peak to peak) 0.1 V/ns

tCHCL(2) Clock Fall Time (peak to peak) 0.1 V/ns

tSLCH tCSS CS# Active Setup Time (relative to SCLK) 3 ns

tCHSL CS# Not Active Hold Time (relative to SCLK) 3 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 2 ns

tCHSH CS# Active Hold Time (relative to SCLK) 3 ns

tSHCH CS# Not Active Setup Time (relative to SCLK) 3 ns

tSHSL tCSH CS# Deselect Time Read 7 ns

Write/Erase/Program 30 ns

tSHQZ(2) tDIS Output Disable Time 8 ns

tCLQV tV Clock Low to Output Valid

Loading: 30pF/15pF

Loading: 30pF 8 ns

Loading: 15pF 6 ns

tCLQX tHO Output Hold Time 1 ns

tWHSL(3) Write Protect Setup Time 20 ns

tSHWL(3) Write Protect Hold Time 100 ns

tDP(2) CS# High to Deep Power-down Mode 10 us

tRES1(2) CS# High to Standby Mode without Electronic Signature

Read 30 us

tRES2(2) CS# High to Standby Mode with Electronic Signature Read 30 us

tW Write Status/Configuration Register Cycle Time 40 ms

tBP Byte-Program 16 30 us

tPP Page Program Cycle Time 0.5 1.5 ms

tPP(5) Page Program Cycle Time (n bytes)

0.008+

(nx0.004)

(6)

1.5 ms

tSE Sector Erase Cycle Time 30 120 ms

tBE32 Block Erase (32KB) Cycle Time 150 650 ms

tBE Block Erase (64KB) Cycle Time 280 650 ms

tCE Chip Erase Cycle Time 50 80 s

tESL(8) Erase Suspend Latency 25 us

tPSL(8) Program Suspend Latency 25 us

tPRS(9) Latency between Program Resume and next Suspend 0.3 100 us

tERS(10) Latency between Erase Resume and next Suspend 0.3 400 us

(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values given for TA=25°C. Not 100% tested.

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Test condition is shown as Figure 79. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL and Figure

80. OUTPUT LOADING.

5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to

program the whole 256 bytes or only a few bytes between 1~256 bytes.

6. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.

7. By default dummy cycle value. Please refer to the Table 1. Read performance Comparison.

8. Latency time required to complete Erase/Program Suspend operation until WIP bit is "0".

9. For tPRS, Min. timing is needed to issue next program suspend command. However, a period of time equal to/

or longer than typ. timing is also required to complete the program progress.

10. For tERS, Min. timing is needed to issue next erase suspend command. However, a period of time equal to/or

longer than typ. timing is also required to complete the erase progress.

xxxxxxxxx Aa /\ _\ /—\ /'"\

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Notes :

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to

Table 17. AC CHARACTERISTICS.

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 500000 us/V

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in Figure 81. AC Timing at Device Power-Up and Figure 82. Power-Down Sequence are for the

supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored,

the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 81. AC Timing at Device Power-Up

SCLK

CS#

VCC

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

tVR

VCC(min)

GND

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

Figure 82. Power-Down Sequence

CS#

SCLK

VCC

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

Figure 83. Power-up Timing

VCC

VCC(min)

Chip Selection is Not Allowed

tVSL

time

Device is fully accessible

VCC(max)

VWI

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

13-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Figure 84. Power Up/Down and Voltage Drop

Table 19. Power-Up/Down Voltage and Timing

Symbol Parameter Min. Max. Unit

tVSL VCC(min.) to device operation 800 us

VWI Write Inhibit Voltage 1.5 2.5 V

VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.9 V

tPWD The minimum duration for ensuring initialization will occur 300 us

VCC VCC Power Supply 2.7 3.6 V

VCC

Time

VCC (max.)

VCC (min.)

tPWD

tVSL

Chip Select is not allowed

Full Device

Access

Allowed

PWD

(max.)

For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing. Please

check the table below for more detail.

Note: These parameters are characterized only.

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

14. ERASE AND PROGRAMMING PERFORMANCE

Note:

1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern.

2. Under worst conditions of 85°C and 2.7V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-

mand.

4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cy-

cle with 90% confidence level.

Parameter Min. Typ. (1) Max. (2) Unit

Write Status Register Cycle Time 40 ms

Sector Erase Cycle Time (4KB) 30 120 ms

Block Erase Cycle Time (32KB) 0.15 0.65 s

Block Erase Cycle Time (64KB) 0.28 0.65 s

Chip Erase Cycle Time 50 80 s

Byte Program Time (via page program command) 16 30 us

Page Program Time 0.5 1.5 ms

Erase/Program Cycle 100,000 cycles

15. DATA RETENTION

Parameter Condition Min. Max. Unit

Data retention 55˚C 20 years

16. LATCH-UP CHARACTERISTICS

Min. Max.

Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax

Input Voltage with respect to GND on SO -1.0V VCC + 1.0V

Current -100mA +100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

MEI—II: MACRDNIX INTERVATIONAL Co., LTD.

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

17. ORDERING INFORMATION

PART NO. CLOCK (MHz) TEMPERATURE PACKAGE Remark

MX25L12835FM2I-10G 104 -40°C to 85°C 8-SOP (200mil)

MX25L12835FMI-10G 104 -40°C to 85°C 16-SOP (300mil)

MX25L12835FZ2I-10G 104 -40°C to 85°C 8-WSON (8x6mm)

MX25L12835FZNI-10G 104 -40°C to 85°C 8-WSON (6x5mm)

MEI—II: MACRDNIX INTERVATIONAL Co., LTD. .2; L 12835F ZZ -1OG

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

18. PART NAME DESCRIPTION

MX 25 L 10Z2 I G

OPTION:

G: RoHS Compliant & Halogen-free

SPEED:

10: 104MHz

TEMPERATURE RANGE:

I: Industrial (-40°C to 85°C)

PACKAGE:

M2: 8-SOP (200mil)

M: 16-SOP (300mil)

ZN: 8-WSON (6x5mm)

Z2: 8-WSON (8x6mm)

DENSITY & MODE:

12835F: 128Mb

TYPE:

L: 3V

DEVICE:

25: Serial Flash

12835F

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD. Doc, 'l‘iile: Package Ouiline for SOP 81. ZOOMIL (ofﬁcial name , 209MIL) "A" L L 4. (L1) .7 DETAIL "A" Dimensions (inch dimensions are derived from the original mm dimensions) \\\SYMBOL \\ A A1 A2 b c D E E1 e L L1 3 9 UNIT \ Min. 1.75 005 170 030 019 5.13 770 5.1a 0.50 121 0.62 0" mm Nom.1.95 015 180 041 020 5.23 790 5.23 127 0.65 131 0.74 5° Max. 216 020 1.91 051 025 533 510 535 000 141 030 0° Min. 0009 0.002 0.067 0.014 0.007 0.202 0303 0.204 0.020 0043 0.024 0“ Inch Nom.0077 0.006 0.071 0.016 0.003 0.200 0311 0.205 0.050 0.026 0052 0.029 5" Max. 0005 0005 0.075 0020 0010 0210 0319 0212 0031 0055 0035 a” .. Reference Dw .Nn. RCVlSlOn g 1mm EIAJ 6110-1406 S

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

19. PACKAGE INFORMATION

19-1. 8-pin SOP (200mil)

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD. Doc. Tillc: Package Outline for SOP 16L (300MIL) i 11 Li .1- Li. 1L. Tﬂ AZA i i A1j - SEATING Dimensions (inch dimensions are derived from the original mm dimensions) \\SYMBOL \\ A A1 A2 h C D E E1 9 L L1 5 9 UNIT Min --- 010 2.25 0.31 0.20 10.10 10.10 7.42 --- 0.40 1.31 0 51 0° mm Nom. --- 0 20 2.35 0.41 0.25 10.30 10.30 7.52 1 27 0.54 1 44 0 64 5" Max 2.65 0 30 2.45 0.51 0.30 10.50 10.50 7.60 "r 1.27 1 57 0 77 8" Min - O 004 0.089 0.012 0 008 0 397 O 397 0.292 --- 0.016 0.052 0 020 0" Inch NOITI. "' 0 008 0 093 0 016 0 010 0 405 0 405 0 295 0 050 0 033 0 057 0 025 5“ Max 0.104 0 012 0.096 0.020 0 012 0 413 0 413 0.299 --- 0.050 0.062 0 030 8" . . Rcfcrcncc Dwg. No. Revlslon JEDEC EIAJ 611071402 13 M87013

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

19-2. 16-pin SOP (300mil)

MEI—II: MACRDNI'X INTERVATIDNAL Co., LTD. Due. Title: Package Outline for WSOD 8L (6x5x0.8MM, LEAD PITCH 1.27MM) I we E E .I J »I«A1 . LASER MARK FOR PIN1 A a—~ IDENTIFICATION IN THIS AREA TOP VIEW SIDE VIEW *1 L ‘9 D1 7I I , J I LE I 7 I F I . i I iPIN 1 INDEX‘AREA BOTTOM VIEW I'”‘I Note ThIs package has an exposed metai pad underneam me package. II I5 recommended Io Ieave me meIaI pad IIoaImg or Io conned II Io me same ground as (he GND pin DHhe package Do nok connect the metaI pad [0 any olhervoliage or sIgnaI IIne on the PCB Avoid pIacing vias orlraces underneath (he meIaI pad Connectmn anhIs melaI pad to any other voiiage or SIgnaI lIne can resuIl m shons and/or eIeoirIoal szmnclion oﬂne devIoe Dimensions (inch dimensions are derived from the original mm dimensions) ‘ \SVMBOL \ s \ A A1 A2 I) D D1 E E1 L e y UNIT \ \ Min. 0 70 -— 0 35 5.90 3 30 4.90 3.90 0 50 0 00 mm Nom. 0 20 0 40 5.00 3 40 5 00 4 00 0 so Max. 0.50 0 05 W 0 45 510 3 50 5.10 4.10 0 75 0 05 Min. 0.025 W -— 0 014 0 232 0129 0.103 0.154 0 020 0 00 Inch Nom. W 0 003 0 01a 0 236 0134 0.197 0.157 0 024 0 05 Max. 0 032 0.002 W 0 019 0 240 0138 0 201 0151 0 030 0.002 . , Reference Dwg. No. Revision JEDEC EIAJ 611073401 8 M07220

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

19-3. 8-land WSON (6x5mm)

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD. Doc. Title: Package Outline for WSON EL (8x6x0.8MM, LEAD PITCH 1.2731“) c D , A2, E LASER MARK FOR PIN 1 N IDENTiFICATiON iN THIS AREA TOP VIEW SIDE VIEW 0 D1 , >L- PIN 1 iNDEX AREA Nate BOTTOM VIEW This package has an exposed meal pad underneain The package. k Is recommended :0 ieave The meal pad ﬂoaiing or id conned ii :0 The same ground as the END pm OHhe package DO ndx conneci me mexai pad to any othervokage or signai iine on me PCB Avoid piacing vias orlraces underneam me meﬁai pad. Cannechun ei ims metal pad to any Dinervuiiage er signai ilne can resuii in shorts and/0r eiecincai maiIundian of me device. Dimensions (inch dimensions are derived from the original mm dimensions) SYMBOL A A1 A2 I: D D1 E E1 L e y UNIT Min. 0 70 0 35 7.90 4 60 5 00 4 50 0.40 0 00 mm Nom. 0 20 0 AD 0 00 4 70 6 00 4 so 0 50 1 27 Max. 0 00 0.05 0 40 0.10 A 00 610 A 70 0.00 0 05 Min. 0 020 0 014 0 311 0101 0 232 0177 0.016 0.00 Inch Nam. 0 000 0 016 0 315 0105 0 235 0101 0 020 0 05 , Max. 0 032 0 002 0 010 0 319 0109 0 240 0105 0 024 0 002 . . Rcfcrcncc Dwg. No, Rcwsmn JEDEC EIAJ 6110-3402 9 M0-220

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

19-4. 8-land WSON (8x6mm)

MEI—II: MACRONI’X INTERVATIDNAL Co., LTD.

100

MX25L12835F

Rev. 1.6, July 22, 2016P/N: PM1795

20. REVISION HISTORY

Revision No. Description Page Date

0.01 1. Added Security Register description P61,62 APR/17/2012

2. Modify the VIH/VIL P88

3. Modify the overshoot from VCC+1.0V or -0.5V to P86

VCC+2.0V or -2.0V

4. Added Fast Boot Sequence P51

5. Modified data retention from 10 years to 20 years P4

6. Added Data Retention P94

7. Corrected content error P44,47,48,52,63,

P65,70,74,77,84

1.0 1. Removed "Advanced Information" P4 OCT/23/2012

2. Modified 16-SOP pin descriptions P7

3. Updated Read/Write Fast Boot Register Sequence figures P52

4. Modified SPB Lock Register table P67

5. Optimize ISB1 & ISB2 spec P88

6. Modified Min. tVSL from 500us to 800us. P93

7. Corrected content error P15,16,21,27~29,30,

P36,50,62,74,88

1.1 1. Modified RESET Timing definition P84 DEC/26/2012

2. Added Power Up/Down and Voltage Drop information P93

3. Corrected content error P9,13,50,62,66,89

1.2 1. Added USPB information P65,71 JUL/16/2013

2. Added note on WP# setup P37

3. Modified tSLCH & tCHSH (Min.) from 5ns to 3.4ns P89

4. Corrected content error P50,51,76,77,

P86,87,89

1.3 1. Updated parameters for DC/AC Characteristics P88,89 OCT/31/2013

2. Updated Erase and Programming Performance P94

3. Content correction P65~71

4. Modified VCC to Ground Potential parameter P86

1.4 1. Added Suspend/Resume symbols and values P75,89,90 SEP/24/2014

2. Description modification P63,65~72

1.5 1. Revised Note of RDSPB and WRSPB figures P69-70 JUL/09/2015

2. Revised Erase Suspend/Write Resume descriptions P74,76

3. Updated BLOCK DIAGRAM P8

1.6 1. Updated tVR values P90,92 JUL/22/2016

2. Updated package outline for 8-WSON P99

3. Updated Write Inhibit Voltage P92

4. Description modification P46-48,56,71

MACROMX INTERNATIONAL Co‘, LTD.

MX25L12835F

101

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

Except for customized products which has been expressly identified in the applicable agreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

household applications only, and not for use in any applications which may, directly or indirectly, cause death,

personal injury, or severe property damages. In the event Macronix products are used in contradicted to their

target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its

actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or

distributors shall be released from any and all liability arisen therefrom.

tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,

NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,

Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au dio, Rich Book, Rich TV, and FitCAM. The names

and brands of third party referred thereto (if any) are for identification purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

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