CY966A0 Series-gegevensblad

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@cvanss
CY96F6A6R
F2MC-16FX CY966A0 Series 16-bit
Proprietary Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-04715 Rev. *C Revised June 21, 2019
CY966A0 series is based on Cypress’s advanced F2MC-16FX architecture (16-bit with instruction pipeline for RISC-like
performance). The CPU uses the same instruction set as the established F2MC-16LX family thus allowing for easy migration of
F2MC-16LX Software to the new F2MC-16FX products. F2MC-16FX product improvements compared to the previous generation
include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up
time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to
32MHz operation frequency from an external 4MHz to 8MHz resonator. The result is a minimum instruction cycle time of 31.2ns
going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the
internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of
the CPU speed.
Features
Technology
0.18m CMOS
CPU
F2MC-16FX CPU
Optimized instruction set for controller applications
(bit, byte, word and long-word data types, 23 different
addressing modes, barrel shift, variety of pointers)
8-byte instruction queue
Signed multiply (16-bit 16-bit) and divide (32-bit/16-bit)
instructions available
System Clock
On-chip PLL clock multiplier (1 to 8, 1 when PLL stop)
4MHz to 8MHz crystal oscillator
(maximum frequency when using ceramic resonator
depends on Q-factor)
Up to 8MHz external clock for devices with fast clock input
feature
32.768kHz subsystem quartz clock
100kHz/2MHz internal RC clock for quick and safe startup,
clock stop detection function, watchdog
Clock source selectable from mainclock oscillator, subclock
oscillator and on-chip RC oscillator, independently for CPU
and 2 clock domains of peripherals
The subclock oscillator is enabled by the Boot ROM program
controlled by a configuration marker after a Power or
External reset
Low Power Consumption - 13 operating modes (different
Run, Sleep, Timer, Stop modes)
On-Chip Voltage Regulator
Internal voltage regulator supports a wide MCU supply
voltage range (Min=2.7V), offering low power consumption
Low Voltage Detection Function
Reset is generated when supply voltage falls below
programmable reference voltage
Code Security
Protects Flash Memory content from unintended read-out
DMA
Automatic transfer function independent of CPU, can be
assigned freely to resources
Interrupts
Fast Interrupt processing
8 programmable priority levels
Non-Maskable Interrupt (NMI)
CAN
Supports CAN protocol version 2.0 part A and B
ISO16845 certified
Bit rates up to 1Mbps
32 message objects
Each message object has its own identifier mask
Programmable FIFO mode (concatenation of message
objects)
Maskable interrupt
Disabled Automatic Retransmission mode for Time Triggered
CAN applications
Programmable loop-back mode for self-test operation
USART
Full duplex USARTs (SCI/LIN)
Document Number: 002-04715 Rev. *C Page 2 of 76
CY96F6A6R
Wide range of baud rate settings using a dedicated reload
timer
Special synchronous options for adapting to different
synchronous serial protocols
LIN functionality working either as master or slave LIN device
Extended support for LIN-Protocol to reduce interrupt load
I2C
Up to 400kbps
Master and Slave functionality, 7-bit and 10-bit addressing
A/D Converter
SAR-type
8/10-bit resolution
Signals interrupt on conversion end, single conversion mode,
continuous conversion mode,
stop conversion mode, activation by software, external
trigger, reload timers and PPGs
Range Comparator Function
Scan Disable Function
ADC Pulse Detection Function
Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit
Main clock timer, 17-bit Sub clock timer)
Hardware Watchdog Timer
Hardware watchdog timer is active after reset
Window function of Watchdog Timer is used to select the
lower window limit of the watchdog interval
Reload Timers
16-bit wide
Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral
clock frequency
Event count function
Free-Running Timers
Signals an interrupt on overflow, supports timer clear upon
match with Output Compare (0, 4)
Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of
peripheral clock frequency
Input Capture Units
16-bit wide
Signals an interrupt upon external event
Rising edge, Falling edge or Both (rising & falling) edges
sensitive
Output Compare Units
16-bit wide
Signals an interrupt when a match with Free-running Timer
occurs
A pair of compare registers can be used to generate an
output signal
Programmable Pulse Generator
16-bit down counter, cycle and duty setting registers
Can be used as 2 8-bit PPG
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock
as counter clock or of selected Reload timer underflow as
clock input
Can be triggered by software or reload timer
Can trigger ADC conversion
Timing point capture
Start delay
Stepping Motor Controller
Stepping Motor Controller with integrated high current output
drivers
Four high current outputs for each channel
Two synchronized 8/10-bit PWMs per channel
Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10,
1/12, 1/16 of peripheral clock
Dedicated power supply for high current output drivers
LCD Controller
LCD controller with up to 4COM 44SEG
Internal or external voltage generation
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
Fixed 1/3 bias
Programmable frame period
Clock source selectable from four options (main clock,
peripheral clock, subclock or RC oscillator clock)
Internal divider resistors or external divider resistors
On-chip data memory for display
LCD display can be operated in Timer Mode
Blank display: selectable
All SEG, COM and V pins can be switched between general
and specialized purposes
Sound Generator
Document Number: 002-04715 Rev. *C Page 3 of 76
CY96F6A6R
8-bit PWM signal is mixed with tone frequency from 16-bit
reload counter
PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral
clock
Real Time Clock
Operational on main oscillation (4MHz), sub oscillation
(32kHz) or RC oscillation (100kHz/2MHz)
Capable to correct oscillation deviation of Sub clock or RC
oscillator clock (clock calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every half
second/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock
External Interrupts
Edge or Level sensitive
Interrupt mask bit per channel
Each available CAN channel RX has an external interrupt for
wake-up
Selected USART channels SIN have an external interrupt for
wake-up
Non Maskable Interrupt
Disabled after reset, can be enabled by Boot-ROM
depending on ROM configuration block
Once enabled, cannot be disabled other than by reset
High or Low level sensitive
Pin shared with external interrupt 0
I/O Ports
Most of the external pins can be used as general purpose I/O
All push-pull outputs (except when used as I2C SDA/SCL
line)
Bit-wise programmable as input/output or peripheral signal
Bit-wise programmable input enable
One input level per GPIO-pin (either Automotive or CMOS
hysteresis)
Bit-wise programmable pull-up resistor
Built-in On Chip Debugger (OCD)
One-wire debug tool interface
Break function
Hardware break: 6 points (shared with code event)
Software break: 4096 points
Event function
Code event: 6 points (shared with hardware break)
Data event: 6 points
Event sequencer: 2 levels + reset
Execution time measurement function
Trace function: 42 branches
Security function
Flash Memory
Dual operation flash allowing reading of one Flash bank
while programming or erasing the other bank
Command sequencer for automatic execution of
programming algorithm and for supporting DMA for
programming of the Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the automatic algorithm
Erase can be performed on each sector individually
Sector protection
Flash Security feature to protect the content of the Flash
Low voltage detection during Flash erase or write
Document Number: 002-04715 Rev. *C Page 4 of 76
CY96F6A6R
Contents
Features ................................................................................................................................................................................... 1
1. Product Lineup .................................................................................................................................................................. 5
2. Block Diagram ................................................................................................................................................................... 6
3. Pin Assignment ................................................................................................................................................................. 7
4. Pin Description .................................................................................................................................................................. 8
5. Pin Circuit Type ............................................................................................................................................................... 10
6. I/O Circuit Type ............................................................................................................................................................... 14
7. Memory Map .................................................................................................................................................................... 21
8. Ramstart Addresses ....................................................................................................................................................... 22
9. User ROM Memory Map for Flash Devices ................................................................................................................... 23
10. Serial Programming Communication Interface ............................................................................................................ 24
11. Interrupt Vector Table ..................................................................................................................................................... 25
12. Handling Precautions ..................................................................................................................................................... 29
12.1 Precautions for Product Design ................................................................................................................................... 29
12.2 Precautions for Package Mounting .............................................................................................................................. 30
12.3 Precautions for Use Environment ................................................................................................................................ 31
13. HANDLING DEVICES ...................................................................................................................................................... 32
14. Electrical Characteristics ............................................................................................................................................... 36
14.1 Absolute Maximum Ratings ......................................................................................................................................... 36
14.2 Recommended Operating Conditions ......................................................................................................................... 39
14.3 DC Characteristics ...................................................................................................................................................... 40
14.3.1 Current Rating .............................................................................................................................................................. 40
14.3.2 Pin Characteristics ....................................................................................................................................................... 43
14.4 AC Characteristics ....................................................................................................................................................... 46
14.4.1 Main Clock Input Characteristics .................................................................................................................................. 46
14.4.2 Sub Clock Input Characteristics ................................................................................................................................... 47
14.4.3 Built-in RC Oscillation Characteristics .......................................................................................................................... 48
14.4.4 Internal Clock Timing ................................................................................................................................................... 48
14.4.5 Operating Conditions of PLL ........................................................................................................................................ 49
14.4.6 Reset Input ................................................................................................................................................................... 49
14.4.7 Power-on Reset Timing ................................................................................................................................................ 50
14.4.8 USART Timing ............................................................................................................................................................. 51
14.4.9 External Input Timing ................................................................................................................................................... 53
14.4.10 I2C Timing ................................................................................................................................................................. 54
14.5 A/D Converter .............................................................................................................................................................. 55
14.5.1 Electrical Characteristics for the A/D Converter ........................................................................................................... 55
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time ......................................................................................... 56
14.5.3 Definition of A/D Converter Terms ............................................................................................................................... 57
14.6 High Current Output Slew Rate ................................................................................................................................... 59
14.7 Low Voltage Detection Function Characteristics ......................................................................................................... 60
14.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 62
15. Example Characteristics ................................................................................................................................................ 63
16. Ordering Information ...................................................................................................................................................... 66
17. Package Dimension ........................................................................................................................................................ 67
18. Major Changes ................................................................................................................................................................ 68
Document History ................................................................................................................................................................. 75
Sales, Solutions, and Legal Information ............................................................................................................................. 76
EMPRESS CY96F6A6R inasunzn II rowunw'
Document Number: 002-04715 Rev. *C Page 5 of 76
CY96F6A6R
1. Product Lineup
Features
Remark
Product Type
Subclock
Dual Operation Flash Memory
RAM
128.5KB + 32KB
8KB
Product Options
R: MCU with CAN
A: MCU without CAN
256.5KB + 32KB
16KB
Package
DMA
USART
LIN-USART 0 to 2/4/5
with automatic LIN-Header
transmission/reception
LIN-USART 0/1
with 16 byte RX- and
TX-FIFO
I2C
I2C 0
8/10-bit A/D Converter
AN 0 to 31
with Data Buffer
with Range Comparator
with Scan Disable
with ADC Pulse Detection
16-bit Reload Timer (RLT)
RLT 0 to 3/6
16-bit Free-Running Timer (FRT)
FRT 0/1
16-bit Input Capture Unit (ICU)
ICU 0 to 7
(ICU 0/1/4 to 6 for LIN-USART)
16-bit Output Compare Unit (OCU)
OCU 0 to 3
8/16-bit Programmable Pulse Generator (PPG)
PPG 0 to 7/12 to 15
with Timing point capture
with Start delay
with Ramp
CAN Interface
CAN 0
32 Message Buffers
Stepping Motor Controller (SMC)
SMC 0 to 4
External Interrupts (INT)
INT 0 to 15
Non-Maskable Interrupt (NMI)
Sound Generator (SG)
SG 0/1
LCD Controller
COM 0 to 3
SEG 0 to 4/7 to 45
Real Time Clock (RTC)
I/O Ports
Clock Calibration Unit (CAL)
Clock Output Function
Low Voltage Detection Function
Low voltage detection function can
be disabled by software
Hardware Watchdog Timer
On-chip RC-oscillator
On-chip Debugger
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the general I/O port according to your function use.
_ CY96F6A6R CYPRESS' A 9* AV n; :1 t: I: t:: + I 0 0 m 0 0 0 : 0 0 0 0 0 0
Document Number: 002-04715 Rev. *C Page 6 of 76
CY96F6A6R
2. Block Diagram
MD
Interrupt
Controller
DMA
Controller
Peripheral Bus 1 (CLKP1)
Peripheral Bus 2 (CLKP2)
I2C
1ch
I/O Timer 1
FRT1
ICU 4/5/6/7
I/O Timer 0
FRT0
ICU 0/1/2/3
OCU 0/1/2/3
16-bit
Reload Timer
0/1/2/3/6
5ch
8/10-bit ADC
32ch
CAN Interface
1ch
USART
5ch
PPG
12ch (16-bit) /
24ch (8-bit)
Real Time
Clock
External
Interrupt
Stepping
Motor
Controller
5ch
Vcc
Vss
PPG0 to PPG7, PPG12 to PPG15
C
Peripheral
Bus Bridge
Peripheral
Bus Bridge
16FX Core Bus (CLKB)
TX0
RX0
Sound
Generator
2ch
SGO0, SGO1, SGO0_R, SGO1_R
SGA0, SGA1, SGA0_R, SGA1_R
SIN0 to SIN2, SIN4, SIN5, SIN5_R
SCK0 to SCK2, SCK4, SCK5, SCK5_R
SOT0 to SOT2, SOT4, SOT5, SOT5_R
SDA0
SCL0
AN0 to AN31
ADTG
TIN1_R, TIN2_R
TIN0 to TIN3
TOT1_R, TOT2_R
TOT0 to TOT3
FRCK0
FRCK1
IN6, IN7
IN4_R to IN7_R
INT0 to INT15
INT1_R to INT7_R
LCD
controller/
driver
4COM × 44SEG
V0 to V3
COM0 to COM3
SEG0 to SEG4
WOT, WOT_R
DVss
TTG0 to TTG7, TTG12 to TTG15
PPG0_R to PPG5_R
PPG0_B to PPG7_B, PPG12_B to PPG15_B
DVcc
PWM1M0 to PWM1M4
PWM1P0 to PWM1P4
PWM2M0 to PWM2M4
PWM2P0 to PWM2P4
IN0, IN1
OUT0_R to OUT3_R
OUT0 to OUT3
FRCK0_R
IN0_R to IN3_R
SEG7 to SEG45
CKOTX0, CKOTX1, CKOTX1_R
CKOT0, CKOT0_R, CKOT1, CKOT1_R
CPU Mode Controller
Clock &
Boot ROMMARWatchdog Voltage
Regulator
16FX Flash
Memory A
NMI
X0, X1
X0A, X1A
RSTX
OCD
DEBUG I/F
AVRL
AVRH
AVss
AVcc
16ch
:iCYPRESS' CY96F6A6R ' EMIinninlumuanw'
Document Number: 002-04715 Rev. *C Page 7 of 76
CY96F6A6R
3. Pin Assignment
(Top view)
(LQM120)
*1: CMOS input level only
*2: CMOS input level only for I2C
*3: Please set ROM Configuration Block (RCB) to use the subclock.
Other than those above, general-purpose pins have only Automotive input level.
LQFP - 120
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
Vss
P00_3 / SEG15 /INT6_R
P00_4 / SEG16 /INT7_R
P00_5 / SEG17 / IN6 / TTG2 / TTG6
P00_6 / SEG18 / IN7 / TTG3 / TTG7
P00_7 / SEG19 / SGO0 / INT14
P01_0 / SEG20 / SGA0
P01_1 / SEG21 /CKOT1 / OUT0
P01_2 / SEG22 /CKOTX1 / OUT1 / INT15
P01_3 / SEG23 / PPG5
P01_4 / SEG24 /SIN4 / INT8*1
P01_5 / SEG25 / SOT4
P01_6 / SEG26 / SCK4 / TTG12*1
P01_7 / SEG27 /CKOTX1_R /INT9 / TTG13
P02_0 / SEG28 /CKOT1_R / INT10 / TTG14
P02_1 / SEG29 /IN6_R / TTG15
P02_2 / SEG30 / IN7_R / CKOT0_R / INT12
P02_3 / SEG31 / SGO0_R / PPG12_B
P02_4 / SEG32 / SGA0_R / PPG13_B
P02_5 / SEG33 / OUT0_R /INT13 / SIN5_R*1
P02_6 / SEG34 / OUT1_R
P02_7 / SEG35 / PPG5_R
P03_0 /V0 / SEG36 / PPG4_B
P03_1 /V1 / SEG37 / PPG5_B
P03_2 /V2 / SEG38 / PPG14_B / SOT5_R
P03_3 /V3 / SEG39 / PPG15_B / SCK5_R*1
P03_4 / RX0 / INT4*1
P03_5 / TX0
P03_6 / INT0 / NMI
Vcc
Vcc
P10_3 / PWM2M4/ PPG7 / AN31
P10_2 / PWM2P4/ SCK2 /PPG6 / AN30*1
P10_1 / PWM1M4 / SOT2 / TOT3 / AN29
P10_0 / PWM1P4 / SIN2 / TIN3 /INT11 / AN28*1
P09_7 / PWM2M3 / PPG15
DVss
DVcc
P09_6 / PWM2P3 / PPG14
P09_5 / PWM1M3 / PPG13
P09_4 / PWM1P3 / PPG12
P09_3 / PWM2M2 / AN27
P09_2 / PWM2P2 / AN26
P09_1 / PWM1M2/ AN25
P09_0 / PWM1P2 / AN24
P08_7 / PWM2M1 / AN23 / PPG7_B
P08_6 / PWM2P1 / AN22 / PPG6_B
P08_5 / PWM1M1 / AN21
DVss
DVcc
P08_4 / PWM1P1 / AN20
P08_3 / PWM2M0 / AN19
P08_2 / PWM2P0 / AN18
P08_1 / PWM1M0 / AN17
P08_0 / PWM1P0 / AN16
P05_7 / AN15 / TOT2 / SGA1_R
P05_6 / AN14 / TIN2 / SGO1_R
P05_5 / AN13
P05_4 / AN12 / INT2_R / WOT_R
Vss
Vcc
P00_2 / SEG14 / INT5_R
P00_1 / SEG13 /INT4_R
P00_0 / SEG12 /INT3_R
P12_7 / SEG11 / INT1_R
P12_6 / SEG10 / TOT2_R /PPG3_B
P12_5 / SEG9 / TIN2_R / PPG2_B
P12_4 / SEG8 / OUT3_R
P12_3 / SEG7 / OUT2_R
P12_2 / TOT1_R / PPG1_B
P12_1 / TIN1_R / PPG0_B
P12_0 / SEG4 / IN1_R
P11_7 / SEG3 / IN0_R
P11_6 / SEG2 / FRCK0_R
P11_5 / SEG1 / PPG4_R
P11_4 / SEG0 / PPG3_R
P11_3 / COM3 / PPG2_R
P11_2 / COM2 / PPG1_R
P11_1 / COM1 / PPG0_R
P11_0 / COM0
RSTX
P04_1 / X1A*3
P04_0 / X0A*3
Vss
X1
X0
MD
P17_0
DEBUG I/F
Vss
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Vss
C
P03_7 / INT1 / SIN1 / SEG40*1
P13_0 / INT2 / SOT1 /SEG41
P13_1 / INT3 / SCK1 / SEG42*1
P13_2 / PPG0 / TIN0 / FRCK1 / SEG43
P13_3 / PPG1 / TOT0 / WOT / SEG44
P13_4 /SIN0 / INT6 / SEG45*1
P13_5 / SOT0 / ADTG / INT7
P13_6 / SCK0 /CKOTX0*1
P13_7 / PPG2 / CKOT0
P04_4 / PPG3 / SDA0*2
P04_5 / PPG4 / SCL0*2
P06_0 / AN0 / IN2_R / SCK5*1
P06_1 / AN1 / IN3_R / SOT5
P06_2 / AN2 / INT5 / SIN5*1
P06_3 / AN3 / FRCK0
P06_4 / AN4 / IN0 / TTG0 / TTG4
P06_5 / AN5 / IN1 / TTG1 / TTG5
P06_6 / AN6 / TIN1 / IN4_R
P06_7 / AN7 / TOT1 / IN5_R
AVcc
AVRH
AVRL
AVss
P05_0 / AN8
P05_1 / AN9
P05_2 / AN10 / OUT2 / SGO1
P05_3 / AN11 / OUT3 / SGA1
Vcc
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
EMPRESS CY96F6A6R inasunzn II rowunw'
Document Number: 002-04715 Rev. *C Page 8 of 76
CY96F6A6R
4. Pin Description
Pin Name
Feature
Description
ADTG
ADC
A/D converter trigger input pin
ANn
ADC
A/D converter channel n input pin
AVcc
Supply
Analog circuits power supply pin
AVRH
ADC
A/D converter high reference voltage input pin
AVRL
ADC
A/D converter low reference voltage input pin
AVss
Supply
Analog circuits power supply pin
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock Output function
Clock Output function n output pin
CKOTn_R
Clock Output function
Relocated Clock Output function n output pin
CKOTXn
Clock Output function
Clock Output function n inverted output pin
CKOTXn_R
Clock Output function
Relocated Clock Output function n inverted output pin
COMn
LCD
LCD Common driver pin
DEBUG I/F
OCD
On Chip Debugger input/output pin
DVcc
Supply
SMC pins power supply
DVss
Supply
SMC pins power supply
FRCKn
Free-Running Timer
Free-Running Timer n input pin
FRCKn_R
Free-Running Timer
Relocated Free-Running Timer n input pin
INn
ICU
Input Capture Unit n input pin
INn_R
ICU
Relocated Input Capture Unit n input pin
INTn
External Interrupt
External Interrupt n input pin
INTn_R
External Interrupt
Relocated External Interrupt n input pin
MD
Core
Input pin for specifying the operating mode
NMI
External Interrupt
Non-Maskable Interrupt input pin
OUTn
OCU
Output Compare Unit n waveform output pin
OUTn_R
OCU
Relocated Output Compare Unit n waveform output pin
Pnn_m
GPIO
General purpose I/O pin
PPGn
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_R
PPG
Relocated Programmable Pulse Generator n output pin (16bit/8bit)
PPGn_B
PPG
Programmable Pulse Generator n output pin (16bit/8bit)
PWMn
SMC
SMC PWM high current output pin
RSTX
Core
Reset input pin
RXn
CAN
CAN interface n RX input pin
SCKn
USART
USART n serial clock input/output pin
SCKn_R
USART
Relocated USART n serial clock input/output pin
SCLn
I2C
I2C interface n clock I/O input/output pin
SDAn
I2C
I2C interface n serial data I/O input/output pin
SEGn
LCD
LCD Segment driver pin
SGAn
Sound Generator
Sound Generator amplitude output pin
SGAn_R
Sound Generator
Relocated Sound Generator amplitude output pin
SGOn
Sound Generator
Sound Generator sound/tone output pin
EMPRESS CY96F6A6R Enasunsn m rowunw'
Document Number: 002-04715 Rev. *C Page 9 of 76
CY96F6A6R
Pin Name
Feature
Description
SGOn_R
Sound Generator
Relocated Sound Generator sound/tone output pin
SINn
USART
USART n serial data input pin
SINn_R
USART
Relocated USART n serial data input pin
SOTn
USART
USART n serial data output pin
SOTn_R
USART
Relocated USART n serial data output pin
TINn
Reload Timer
Reload Timer n event input pin
TINn_R
Reload Timer
Relocated Reload Timer n event input pin
TOTn
Reload Timer
Reload Timer n output pin
TOTn_R
Reload Timer
Relocated Reload Timer n output pin
TTGn
PPG
Programmable Pulse Generator n trigger input pin
TXn
CAN
CAN interface n TX output pin
Vn
LCD
LCD voltage reference pin
Vcc
Supply
Power supply pin
Vss
Supply
Power supply pin
WOT
RTC
Real Time clock output pin
WOT_R
RTC
Relocated Real Time clock output pin
X0
Clock
Oscillator input pin
X0A
Clock
Subclock Oscillator input pin
X1
Clock
Oscillator output pin
X1A
Clock
Subclock Oscillator output pin
EMPRESS CY96F6A6R inasunzn II rowunw'
Document Number: 002-04715 Rev. *C Page 10 of 76
CY96F6A6R
5. Pin Circuit Type
Pin No.
I/O Circuit Type*
Pin Name
1
Supply
Vss
2
F
C
3
P
P03_7 / INT1 / SIN1 / SEG40
4
J
P13_0 / INT2 / SOT1 / SEG41
5
P
P13_1 / INT3 / SCK1 / SEG42
6
J
P13_2 / PPG0 / TIN0 / FRCK1 / SEG43
7
J
P13_3 / PPG1 / TOT0 / WOT / SEG44
8
P
P13_4 / SIN0 / INT6 / SEG45
9
H
P13_5 / SOT0 / ADTG / INT7
10
M
P13_6 / SCK0 / CKOTX0
11
H
P13_7 / PPG2 / CKOT0
12
N
P04_4 / PPG3 / SDA0
13
N
P04_5 / PPG4 / SCL0
14
I
P06_0 / AN0 / IN2_R / SCK5
15
K
P06_1 / AN1 / IN3_R / SOT5
16
I
P06_2 / AN2 / INT5 / SIN5
17
K
P06_3 / AN3 / FRCK0
18
K
P06_4 / AN4 / IN0 / TTG0 / TTG4
19
K
P06_5 / AN5 / IN1 / TTG1 / TTG5
20
K
P06_6 / AN6 / TIN1 / IN4_R
21
K
P06_7 / AN7 / TOT1 / IN5_R
22
Supply
AVcc
23
G
AVRH
24
G
AVRL
25
Supply
AVss
26
K
P05_0 / AN8
27
K
P05_1 / AN9
28
K
P05_2 / AN10 / OUT2 / SGO1
29
K
P05_3 / AN11 / OUT3 / SGA1
30
Supply
Vcc
31
Supply
Vss
32
K
P05_4 / AN12 / INT2_R / WOT_R
33
K
P05_5 / AN13
34
K
P05_6 / AN14 / TIN2 / SGO1_R
35
K
P05_7 / AN15 / TOT2 / SGA1_R
36
R
P08_0 / PWM1P0 / AN16
37
R
P08_1 / PWM1M0 / AN17
:iCYPRESS' CY96F6A6R ' EHaEunEnmmwunw
Document Number: 002-04715 Rev. *C Page 11 of 76
CY96F6A6R
Pin No.
I/O Circuit Type*
Pin Name
38
R
P08_2 / PWM2P0 / AN18
39
R
P08_3 / PWM2M0 / AN19
40
R
P08_4 / PWM1P1 / AN20
41
Supply
DVcc
42
Supply
DVss
43
R
P08_5 / PWM1M1 / AN21
44
R
P08_6 / PWM2P1 / AN22 / PPG6_B
45
R
P08_7 / PWM2M1 / AN23 / PPG7_B
46
R
P09_0 / PWM1P2 / AN24
47
R
P09_1 / PWM1M2 / AN25
48
R
P09_2 / PWM2P2 / AN26
49
R
P09_3 / PWM2M2 / AN27
50
T
P09_4 / PWM1P3 / PPG12
51
T
P09_5 / PWM1M3 / PPG13
52
T
P09_6 / PWM2P3 / PPG14
53
Supply
DVcc
54
Supply
DVss
55
T
P09_7 / PWM2M3 / PPG15
56
S
P10_0 / PWM1P4 / SIN2 / TIN3 / INT11 / AN28
57
R
P10_1 / PWM1M4 / SOT2 / TOT3 / AN29
58
S
P10_2 / PWM2P4 / SCK2 / PPG6 / AN30
59
R
P10_3 / PWM2M4 / PPG7 / AN31
60
Supply
Vcc
61
Supply
Vss
62
O
DEBUG I/F
63
H
P17_0
64
C
MD
65
A
X0
66
A
X1
67
Supply
Vss
68
B
P04_0 / X0A
69
B
P04_1 / X1A
70
C
RSTX
71
J
P11_0 / COM0
72
J
P11_1 / COM1 / PPG0_R
73
J
P11_2 / COM2 / PPG1_R
74
J
P11_3 / COM3 / PPG2_R
75
J
P11_4 / SEG0 / PPG3_R
76
J
P11_5 / SEG1 / PPG4_R
:iCYPRESS' CY96F6A6R ' EHaEunEnmmwunw
Document Number: 002-04715 Rev. *C Page 12 of 76
CY96F6A6R
Pin No.
I/O Circuit Type*
Pin Name
77
J
P11_6 / SEG2 / FRCK0_R
78
J
P11_7 / SEG3 / IN0_R
79
J
P12_0 / SEG4 / IN1_R
80
H
P12_1 / TIN1_R / PPG0_B
81
H
P12_2 / TOT1_R / PPG1_B
82
J
P12_3 / SEG7 / OUT2_R
83
J
P12_4 / SEG8 / OUT3_R
84
J
P12_5 / SEG9 / TIN2_R / PPG2_B
85
J
P12_6 / SEG10 / TOT2_R / PPG3_B
86
J
P12_7 / SEG11 / INT1_R
87
J
P00_0 / SEG12 / INT3_R
88
J
P00_1 / SEG13 / INT4_R
89
J
P00_2 / SEG14 / INT5_R
90
Supply
Vcc
91
Supply
Vss
92
J
P00_3 / SEG15 / INT6_R
93
J
P00_4 / SEG16 / INT7_R
94
J
P00_5 / SEG17 / IN6 / TTG2 / TTG6
95
J
P00_6 / SEG18 / IN7 / TTG3 / TTG7
96
J
P00_7 / SEG19 / SGO0 / INT14
97
J
P01_0 / SEG20 / SGA0
98
J
P01_1 / SEG21 / CKOT1 / OUT0
99
J
P01_2 / SEG22 / CKOTX1 / OUT1 / INT15
100
J
P01_3 / SEG23 / PPG5
101
P
P01_4 / SEG24 / SIN4 / INT8
102
J
P01_5 / SEG25 / SOT4
103
P
P01_6 / SEG26 / SCK4 / TTG12
104
J
P01_7 / SEG27 / CKOTX1_R / INT9 / TTG13
105
J
P02_0 / SEG28 / CKOT1_R / INT10 / TTG14
106
J
P02_1 / SEG29 / IN6_R / TTG15
107
J
P02_2 / SEG30 / IN7_R / CKOT0_R / INT12
108
J
P02_3 / SEG31 / SGO0_R / PPG12_B
109
J
P02_4 / SEG32 / SGA0_R / PPG13_B
110
P
P02_5 / SEG33 / OUT0_R / INT13 / SIN5_R
111
J
P02_6 / SEG34 / OUT1_R
112
J
P02_7 / SEG35 / PPG5_R
113
L
P03_0 / V0 / SEG36 / PPG4_B
114
L
P03_1 / V1 / SEG37 / PPG5_B
115
L
P03_2 / V2 / SEG38 / PPG14_B / SOT5_R
:iCYPRESS' CY96F6A6R ' sM-snnsnumumw
Document Number: 002-04715 Rev. *C Page 13 of 76
CY96F6A6R
*: See “I/O Circuit Type” for details on the I/O circuit types.
Pin No.
I/O Circuit Type*
Pin Name
116
Q
P03_3 / V3 / SEG39 / PPG15_B / SCK5_R
117
M
P03_4 / RX0 / INT4
118
H
P03_5 / TX0
119
H
P03_6 / INT0 / NMI
120
Supply
Vcc
X17 % “ HZ: Y7
Document Number: 002-04715 Rev. *C Page 14 of 76
CY96F6A6R
6. I/O Circuit Type
Type
Circuit
Remarks
A
High-speed oscillation circuit:
Programmable between
oscillation mode (external
crystal or resonator connected
to X0/X1 pins) and Fast
external Clock Input (FCI)
mode (external clock
connected to X0 pin)
Feedback resistor = approx.
1.0M
The amplitude: 1.8V±0.15V
to operate by the internal
supply voltage
R
FCI
X out
0
1
X1
X0
FCI or Osc disable
:iCYPRESS' CY96F6A6R nnnnnnnnnnnnnnnnnnn X1A XOA gimresis
Document Number: 002-04715 Rev. *C Page 15 of 76
CY96F6A6R
Type
Circuit
Remarks
B
Low-speed oscillation circuit shared
with GPIO functionality:
Feedback resistor = approx.
5.0M
GPIO functionality selectable
(CMOS level output (IOL =
4mA, IOH = -4mA), Automotive
input with input shutdown
function and programmable
pull-up resistor)
C
CMOS hysteresis input pin
R
FCI
X out
0
1
Pout
R
Nout
Automotive input
FCI or Osc disable
Standby
control
for input
shutdown
Standby
control
for input
shutdown
Automotive input
X1A
X0A
R
P-ch P-ch
N-ch
Pull-up control
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
L
Document Number: 002-04715 Rev. *C Page 16 of 76
CY96F6A6R
Type
Circuit
Remarks
F
Power supply input protection circuit
G
A/D converter ref+ (AVRH)/
ref- (AVRL) power supply input
pin with protection circuit
Without protection circuit
against VCC for pins
AVRH/AVRL
H
CMOS level output
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up resistor
I
CMOS level output
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up resistor
Analog input
P-ch
N-ch
P-ch
N-ch
Standby control
for input shutdown Automotive input
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Analog input
Hysteresis input
ficvanss CY96F6A6R nnnnnnnnnnnnnnnnnnn
Document Number: 002-04715 Rev. *C Page 17 of 76
CY96F6A6R
Type
Circuit
Remarks
J
CMOS level output
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up resistor
SEG or COM output
K
CMOS level output
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up resistor
Analog input
L
CMOS level output
(IOL = 4mA, IOH = -4mA)
Automotive input with input
shutdown function
Programmable pull-up resistor
Vn input or SEG output
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
SEG or COM output
Automotive input
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Analog input
Automotive input
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Vn input or SEG output
Automotive input
ficvanss CY96F6A6R nnnnnnnnnnnnnnnnnnn
Document Number: 002-04715 Rev. *C Page 18 of 76
CY96F6A6R
Type
Circuit
Remarks
M
CMOS level output
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up resistor
N
CMOS level output
(IOL = 3mA, IOH = -3mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up resistor
*: N-channel transistor has slew
rate control according to I2C
spec, irrespective of usage.
O
Open-drain I/O
Output 25mA, Vcc = 2.7V
TTL input
Standby control
for input shutdown
Hysteresis input
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Standby control
for input shutdown
Hysteresis input
R
Pull-up control
Pout
Nout*
P-ch P-ch
N-ch
Standby control
for input shutdown TTL input
R
Nout
N-ch
Document Number: 002-04715 Rev. *C Page 19 of 76
CY96F6A6R
Type
Circuit
Remarks
P
CMOS level output
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis inputs with
input shutdown function
Programmable pull-up resistor
SEG or COM output
Q
CMOS level output
(IOL = 4mA, IOH = -4mA)
CMOS hysteresis inputs with
input shutdown function
Programmable pull-up resistor
Vn input or SEG output
R
CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
Automotive input with input
shutdown function
Programmable pull-up /
pull-down resistor
Analog input
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
SEG or COM output
Hysteresis input
Standby control
for input shutdown
R
Pull-up control
Pout
Nout
P-ch P-ch
N-ch
Vn input or SEG output
Hysteresis input
Standby control
for input shutdown
R
Pull-up control
Pull-down control
Pout
Nout
P-ch P-ch
N-ch
N-ch
Analog input
Automotive input
:iCYPRESS' CY96F6A6R nnnnnnnnnnnnnnnnnnn
Document Number: 002-04715 Rev. *C Page 20 of 76
CY96F6A6R
Type
Circuit
Remarks
S
CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
CMOS hysteresis input with
input shutdown function
Programmable pull-up /
pull-down resistor
Analog input
T
CMOS level output
(programmable IOL = 4mA,
IOH = -4mA and IOL = 30mA,
IOH = -30mA)
Automotive input with input
shutdown function
Programmable pull-up /
pull-down resistor
Standby control
for input shutdown
R
Pull-up control
Pull-down control
Pout
Nout
P-ch P-ch
N-ch
N-ch
Analog input
Hysteresis input
Standby control
for input shutdown
R
Pull-up control
Pull-down control
Pout
Nout
P-ch P-ch
N-ch
N-ch
Automotive input
@glPRESS' CY96F6A6R m m mumr
Document Number: 002-04715 Rev. *C Page 21 of 76
CY96F6A6R
7. Memory Map
*1: For details about USER ROM area, see “User ROM Memory Map For Flash Devices” on the following pages.
*2: For RAMSTART addresses, see the table on the next page.
*3: Unused GPR banks can be used as RAM area.
GPR: General-Purpose Register
The DMA area is only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
FF:FFFFH
DE:0000H
DD:FFFFH
10:0000H
0F:C000H
0E:9000H
01:0000H
00:8000H
RAMSTART0*2
00:0C00H
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
GPR*3
DMA
Reserved
Peripheral
Reserved
USER ROM*1
Reserved
Boot-ROM
Peripheral
ROM/RAM
MIRROR
Internal RAM
bank0
Peripheral
Reserved
:iCYPRESS' ' EMlinninlumuanw' Bank 0 RAM Sixe CY96F6A6R
Document Number: 002-04715 Rev. *C Page 22 of 76
CY96F6A6R
8. Ramstart Addresses
Devices
Bank 0
RAM Size
RAMSTART0
CY96F6A5
8KB
00:6200H
CY96F6A6
16KB
00:4200H
CYPRESS‘ ' EMaEnnEnmmMaunw' CY96F6A6R Bank A of Hash A CY96F6A5 CY96F6A6 CPU made Hash memory Hash size Hash srza address made address 128 5K3 + mm 256 SKB v 22KB FF FFFFH 3F FFFFi , , FF 0000“ SF 0000“ sAae 54KB sAae 64KB FE FFFFH 3E FFFFi FE MUN SE 0000» sAaa , 54KB SA38 , 64KB FD FFFFN 3D FFFFN 5A3? , 64KB FD 0mmN 3D 0mmN FC FFFFH ac FFFFN , 4 PC 0000H ac 0mmN SA36 6 KB FE FFFFN Reserved Reserved DF A000N DF SFFFH 1F SFFFN 8A4 78KB 8A4 78KB DF mmN 1F sumN DF 7FFFN 1F 7FFFN 8A3 , BKE 5A3 , 5K3 DF 6mmN 1F 6mmN DF 5FFFN 1F 5FFFN DF 4mmH 1F 4000H 8A2 V BKE 8A2 7 am DF aFFFN 1F aFFFN DF 2mm“ 1F 2000“ SN BKE SN 8K8 DF WP“ 1F ”FF“ SAS , 5123* SAS , 5128‘ DF 0mmN 1F 0mmN DE FFFF “ Reserved Reserved DE 0mm Bank B of Hash A Bank A of Hash A
Document Number: 002-04715 Rev. *C Page 23 of 76
CY96F6A6R
9. User ROM Memory Map for Flash Devices
*: Physical address area of SAS-512B is from DF:0000H to DF:01FFH.
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
Sector SAS contains the ROM configuration block RCBA at CPU address DF:0000H -DF:01FFH.
SAS can not be used for E2PROM emulation.
:iCYPRESS' CY96F6A6R ' mmnsnumumnw-
Document Number: 002-04715 Rev. *C Page 24 of 76
CY96F6A6R
10. Serial Programming Communication Interface
USART pins for Flash serial programming (MD = 0, DEBUG I/F = 0, Serial Communication mode)
CY966A0
Pin Number
USART Number
Normal Function
8
USART0
SIN0
9
SOT0
10
SCK0
3
USART1
SIN1
4
SOT1
5
SCK1
56
USART2
SIN2
57
SOT2
58
SCK2
101
USART4
SIN4
102
SOT4
103
SCK4
:iCYPRESS' CY96F6A6R ' EHaEunEnmmwunw Vector Cleared by
Document Number: 002-04715 Rev. *C Page 25 of 76
CY96F6A6R
11. Interrupt Vector Table
Vector
Number
Offset in
Vector Table
Vector Name
Cleared by
DMA
Index in
ICR to
Program
Description
0
3FCH
CALLV0
No
-
CALLV instruction
1
3F8H
CALLV1
No
-
CALLV instruction
2
3F4H
CALLV2
No
-
CALLV instruction
3
3F0H
CALLV3
No
-
CALLV instruction
4
3ECH
CALLV4
No
-
CALLV instruction
5
3E8H
CALLV5
No
-
CALLV instruction
6
3E4H
CALLV6
No
-
CALLV instruction
7
3E0H
CALLV7
No
-
CALLV instruction
8
3DCH
RESET
No
-
Reset vector
9
3D8H
INT9
No
-
INT9 instruction
10
3D4H
EXCEPTION
No
-
Undefined instruction execution
11
3D0H
NMI
No
-
Non-Maskable Interrupt
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Clock Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
LVDI
No
16
Low Voltage Detector
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
EXTINT5
Yes
22
External Interrupt 5
23
3A0H
EXTINT6
Yes
23
External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
EXTINT8
Yes
25
External Interrupt 8
26
394H
EXTINT9
Yes
26
External Interrupt 9
27
390H
EXTINT10
Yes
27
External Interrupt 10
28
38CH
EXTINT11
Yes
28
External Interrupt 11
29
388H
EXTINT12
Yes
29
External Interrupt 12
30
384H
EXTINT13
Yes
30
External Interrupt 13
31
380H
EXTINT14
Yes
31
External Interrupt 14
32
37CH
EXTINT15
Yes
32
External Interrupt 15
33
378H
CAN0
No
33
CAN Controller 0
34
374H
-
-
34
Reserved
35
370H
-
-
35
Reserved
36
36CH
-
-
36
Reserved
37
368H
-
-
37
Reserved
38
364H
PPG0
Yes
38
Programmable Pulse Generator 0
39
360H
PPG1
Yes
39
Programmable Pulse Generator 1
:iCYPRESS' CY96F6A6R inasunzn II rowunw' Vector Cleared by
Document Number: 002-04715 Rev. *C Page 26 of 76
CY96F6A6R
Vector
Number
Offset in
Vector Table
Vector Name
Cleared by
DMA
Index in
ICR to
Program
Description
40
35CH
PPG2
Yes
40
Programmable Pulse Generator 2
41
358H
PPG3
Yes
41
Programmable Pulse Generator 3
42
354H
PPG4
Yes
42
Programmable Pulse Generator 4
43
350H
PPG5
Yes
43
Programmable Pulse Generator 5
44
34CH
PPG6
Yes
44
Programmable Pulse Generator 6
45
348H
PPG7
Yes
45
Programmable Pulse Generator 7
46
344H
-
-
46
Reserved
47
340H
-
-
47
Reserved
48
33CH
-
-
48
Reserved
49
338H
-
-
49
Reserved
50
334H
PPG12
Yes
50
Programmable Pulse Generator 12
51
330H
PPG13
Yes
51
Programmable Pulse Generator 13
52
32CH
PPG14
Yes
52
Programmable Pulse Generator 14
53
328H
PPG15
Yes
53
Programmable Pulse Generator 15
54
324H
-
-
54
Reserved
55
320H
-
-
55
Reserved
56
31CH
-
-
56
Reserved
57
318H
-
-
57
Reserved
58
314H
RLT0
Yes
58
Reload Timer 0
59
310H
RLT1
Yes
59
Reload Timer 1
60
30CH
RLT2
Yes
60
Reload Timer 2
61
308H
RLT3
Yes
61
Reload Timer 3
62
304H
-
-
62
Reserved
63
300H
-
-
63
Reserved
64
2FCH
RLT6
Yes
64
Reload Timer 6
65
2F8H
ICU0
Yes
65
Input Capture Unit 0
66
2F4H
ICU1
Yes
66
Input Capture Unit 1
67
2F0H
ICU2
Yes
67
Input Capture Unit 2
68
2ECH
ICU3
Yes
68
Input Capture Unit 3
69
2E8H
ICU4
Yes
69
Input Capture Unit 4
70
2E4H
ICU5
Yes
70
Input Capture Unit 5
71
2E0H
ICU6
Yes
71
Input Capture Unit 6
72
2DCH
ICU7
Yes
72
Input Capture Unit 7
73
2D8H
-
-
73
Reserved
74
2D4H
-
-
74
Reserved
75
2D0H
-
-
75
Reserved
76
2CCH
-
-
76
Reserved
77
2C8H
OCU0
Yes
77
Output Compare Unit 0
:iCYPRESS' CY96F6A6R inasunzn II rowunw' Vector Cleared by
Document Number: 002-04715 Rev. *C Page 27 of 76
CY96F6A6R
Vector
Number
Offset in
Vector Table
Vector Name
Cleared by
DMA
Index in
ICR to
Program
Description
78
2C4H
OCU1
Yes
78
Output Compare Unit 1
79
2C0H
OCU2
Yes
79
Output Compare Unit 2
80
2BCH
OCU3
Yes
80
Output Compare Unit 3
81
2B8H
-
-
81
Reserved
82
2B4H
-
-
82
Reserved
83
2B0H
-
-
83
Reserved
84
2ACH
-
-
84
Reserved
85
2A8H
-
-
85
Reserved
86
2A4H
-
-
86
Reserved
87
2A0H
-
-
87
Reserved
88
29CH
-
-
88
Reserved
89
298H
FRT0
Yes
89
Free-Running Timer 0
90
294H
FRT1
Yes
90
Free-Running Timer 1
91
290H
-
-
91
Reserved
92
28CH
-
-
92
Reserved
93
288H
RTC0
No
93
Real Time Clock
94
284H
CAL0
No
94
Clock Calibration Unit
95
280H
SG0
No
95
Sound Generator 0
96
27CH
IIC0
Yes
96
I2C interface 0
97
278H
-
-
97
Reserved
98
274H
ADC0
Yes
98
A/D Converter 0
99
270H
-
-
99
Reserved
100
26CH
-
-
100
Reserved
101
268H
LINR0
Yes
101
LIN USART 0 RX
102
264H
LINT0
Yes
102
LIN USART 0 TX
103
260H
LINR1
Yes
103
LIN USART 1 RX
104
25CH
LINT1
Yes
104
LIN USART 1 TX
105
258H
LINR2
Yes
105
LIN USART 2 RX
106
254H
LINT2
Yes
106
LIN USART 2 TX
107
250H
-
-
107
Reserved
108
24CH
-
-
108
Reserved
109
248H
LINR4
Yes
109
LIN USART 4 RX
110
244H
LINT4
Yes
110
LIN USART 4 TX
111
240H
LINR5
Yes
111
LIN USART 5 RX
112
23CH
LINT5
Yes
112
LIN USART 5 TX
113
238H
-
-
113
Reserved
114
234H
-
-
114
Reserved
115
230H
-
-
115
Reserved
:iCYPRESS' CY96F6A6R inasunzn II rowunw' Vector Cleared by
Document Number: 002-04715 Rev. *C Page 28 of 76
CY96F6A6R
Vector
Number
Offset in
Vector Table
Vector Name
Cleared by
DMA
Index in
ICR to
Program
Description
116
22CH
-
-
116
Reserved
117
228H
-
-
117
Reserved
118
224H
-
-
118
Reserved
119
220H
-
-
119
Reserved
120
21CH
-
-
120
Reserved
121
218H
SG1
No
121
Sound Generator 1
122
214H
-
-
122
Reserved
123
210H
-
-
123
Reserved
124
20CH
-
-
124
Reserved
125
208H
-
-
125
Reserved
126
204H
-
-
126
Reserved
127
200H
-
-
127
Reserved
128
1FCH
-
-
128
Reserved
129
1F8H
-
-
129
Reserved
130
1F4H
-
-
130
Reserved
131
1F0H
-
-
131
Reserved
132
1ECH
-
-
132
Reserved
133
1E8H
FLASHA
Yes
133
Flash memory A interrupt
134
1E4H
-
-
134
Reserved
135
1E0H
-
-
135
Reserved
136
1DCH
-
-
136
Reserved
137
1D8H
-
-
137
Reserved
138
1D4H
-
-
138
Reserved
139
1D0H
ADCRC0
No
139
A/D Converter 0 - Range Comparator
140
1CCH
ADCPD0
No
140
A/D Converter 0 - Pulse detection
141
1C8H
-
-
141
Reserved
142
1C4H
-
-
142
Reserved
143
1C0H
-
-
143
Reserved
Document Number: 002-04715 Rev. *C Page 29 of 76
CY96F6A6R
12. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
12.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the
device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current
conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current
flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to
abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current
levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to
abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04715 Rev. *C Page 30 of 76
CY96F6A6R
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for
damages arising from such use without prior approval.
12.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to Cypress mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction
strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between
5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04715 Rev. *C Page 31 of 76
CY96F6A6R
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation
may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the
level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
12.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels
are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such
cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the
device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If
devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04715 Rev. *C Page 32 of 76
CY96F6A6R
13. HANDLING DEVICES
Special Care is Required for the following when Handling the Device:
• Latch-up prevention
• Unused pins handling
• External clock usage
• Notes on PLL clock mode operation
• Power supply pins (Vcc/Vss)
• Crystal oscillator and ceramic resonator circuit
• Turn on sequence of power supply to A/D converter and analog inputs
• Pin handling when not using the A/D converter
• Notes on Power-on
• Stabilization of power supply voltage
• SMC power supply pins
• Serial communication
• Mode Pin (MD)
1. Latch-Up Prevention
CMOS IC chips may suffer latch-up under the following conditions:
- A voltage higher than VCC or lower than VSS is applied to an input or output pin.
- A voltage higher than the rated voltage is applied between Vcc pins and Vss pins.
- The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused Pins Handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. To prevent latch-up, they must therefore be pulled up or pulled down through resistors which should be
more than 2k..
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External Clock Usage
The permitted frequency range of an external clock depends on the oscillator type and configuration.
See AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks must be connected as
follows:
(1) Single Phase External Clock for Main Oscillator
When using a single phase external clock for the Main oscillator, X0 pin must be driven and X1 pin left open.
And supply 1.8V power to the external clock.
Document Number: 002-04715 Rev. *C Page 33 of 76
CY96F6A6R
X0
X1
Document Number: 002-04715 Rev. *C Page 34 of 76
CY96F6A6R
(2) Single Phase External Clock for Sub Oscillator
When using a single phase external clock for the Sub oscillator, “External clock mode” must be selected and
X0A/P04_0 pin must be driven. X1A/P04_1 pin can be configured as GPIO.
(3) Opposite Phase External Clock
When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has
the opposite phase to the X0 (X0A) pins. Supply level on X0 and X1 pins must be 1.8V.
4. Notes on PLL Clock Mode Operation
If the microcontroller is operated with PLL clock mode and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot be guaranteed.
5. Power Supply Pins (Vcc/Vss)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more than one VCC or
VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating range.
Vcc and Vss pins must be connected to the device from the power supply with lowest possible impedance.
The smoothing capacitor at Vcc pin must use the one of a capacity value that is larger than Cs.
Besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1F between Vcc
and Vss pins as close as possible to Vcc and Vss pins.
6. Crystal Oscillator and ceramic resonator Circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors with shortest
possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost
effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins with a ground area
for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator manufacturer,
especially when using low-Q resonators at higher frequencies.
7. Turn on Sequence of Power Supply to A/D Converter and Analog Inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after turning the digital
power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this case, AVRH must
not exceed AVCC . Input voltage for ports shared with analog input ports also must not exceed AVCC (turning the analog and digital
power supplies simultaneously on or off is acceptable).
8. Pin Handling when not using the A/D Converter
If the A/D converter is not used, the power supply pins for A/D converter should be connected such as AVCC = VCC, AVSS = AVRH
=AVRL = VSS.
X0
X1
Document Number: 002-04715 Rev. *C Page 35 of 76
CY96F6A6R
9. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower
than 50s from 0.2V to 2.7V.
10. Stabilization of Power Supply Voltage
If the power supply voltage varies acutely even within the operation safety range of the VCC power supply voltage, a malfunction
may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, the power supply voltage must
be stabilized in such a way that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50Hz to 60Hz) fall
within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/s or less in instantaneous
fluctuation for power supply switching.
11. SMC Power Supply Pins
All DVcc /DVss pins must be set to the same level as the Vcc /Vss pins.
Note that the SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, VCC must always be
powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
12. Serial Communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
13. Mode Pin (MD)
Connect the mode pin directly to Vcc or Vss pin. To prevent the device unintentionally entering test mode due to noise, lay out the
printed circuit board so as to minimize the distance from the mode pin to Vcc or Vss pin and provide a low-impedance connection.
:iCYPRESS' CY96F6A6R inasunzn m rowunw' m uLsMc ow uwsmc OH OHSMC ow uHAvSMc u
Document Number: 002-04715 Rev. *C Page 36 of 76
CY96F6A6R
14. Electrical Characteristics
14.1 Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Remarks
Min
Max
Power supply voltage*1
VCC
-
VSS - 0.3
VSS + 6.0
V
Analog power supply
voltage*1
AVCC
-
VSS - 0.3
VSS + 6.0
V
VCC = AVCC*2
Analog reference
voltage*1
AVRH,
AVRL
-
VSS - 0.3
VSS + 6.0
V
AVCC≥ AVRH,
AVCC ≥ AVRL,
AVRH > AVRL,
AVRL ≥ AVSS
SMC Power supply*1
DVCC
-
VSS - 0.3
VSS + 6.0
V
VCC = AVCC= DVCC*2
LCD power supply
voltage*1
V0 to V3
-
VSS - 0.3
VSS + 6.0
V
V0 to V3 must not exceed
VCC
Input voltage*1
VI
-
VSS - 0.3
VSS + 6.0
V
VI ≤ (D)VCC + 0.3V*3
Output voltage*1
VO
-
VSS - 0.3
VSS + 6.0
V
VO ≤ (D)VCC + 0.3V*3
Maximum Clamp
Current
ICLAMP
-
-4.0
+4.0
mA
Applicable to general
purpose I/O pins *4
Total Maximum Clamp
Current
Σ|ICLAMP|
-
-
32
mA
Applicable to general
purpose I/O pins *4
"L" level maximum
output current
IOL
-
-
15
mA
Normal port
IOLSMC
TA= -40°C
-
52
mA
High current port
TA= +25°C
-
39
mA
TA= +85°C
-
32
mA
TA= +105°C
-
30
mA
"L" level average output
current
IOLAV
-
-
4
mA
Normal port
IOLAVSMC
TA= -40°C
-
40
mA
High current port
TA= +25°C
-
30
mA
TA= +85°C
-
25
mA
TA= +105°C
-
23
mA
"L" level maximum
overall output current
ΣIOL
-
-
62
mA
Normal port
ΣIOLSMC
-
-
300
mA
High current port
"L" level average overall
output current
ΣIOLAV
-
-
31
mA
Normal port
ΣIOLAVSMC
-
-
210
mA
High current port
"H" level maximum
output current
IOH
-
-
-15
mA
Normal port
IOHSMC
TA= -40°C
-
-52
mA
High current port
TA= +25°C
-
-39
mA
TA= +85°C
-
-32
mA
TA= +105°C
-
-30
mA
"H" level average output
current
IOHAV
-
-
-4
mA
Normal port
IOHAVSMC
TA= -40°C
-
-40
mA
High current port
TA= +25°C
-
-30
mA
TA= +85°C
-
-25
mA
TA= +105°C
-
-23
mA
"H" level maximum
overall output current
ΣIOH
-
-
-62
mA
Normal port
ΣIOHSMC
-
-
-300
mA
High current port
"H" level average
overall output current
ΣIOHAV
-
-
-31
mA
Normal port
ΣIOHAVSMC
-
-
-210
mA
High current port
Power consumption*5
PD
TA= +105°C
-
357*6
mW
Operating ambient
temperature
TA
-
-40
+105
°C
Storage temperature
TSTG
-
-55
+150
°C
*1: This parameter is based on VSS = AVSS = DVSS = 0V.
*2: AVCC and VCC and DVCC must be set to the same voltage. It is required that AVCC does not exceed VCC, DVCC and that the
voltage at the analog inputs does not exceed AVCC when the power is switched on.
*3: VI and VO should not exceed VCC + 0.3V. VI should also not exceed the specified ratings. However if the maximum current
to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/Output
voltages of high current ports depend on DVCC. Input/Output voltages of standard ports depend on VCC.
*4: • Applicable to all general purpose I/O pins (Pnn_m).
• Use within recommended operating conditions.
Document Number: 002-04715 Rev. *C Page 37 of 76
CY96F6A6R
• Use at DC voltage (current).
• The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the
microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided
from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply
voltage may not be sufficient to operate the Power reset.
• The DEBUG I/F pin has only a protective diode against VSS. Hence it is only permitted to input a negative clamping current
(4mA). For protection against positive input voltages, use an external clamping diode which limits the input voltage to
maximum 6.0V.
Document Number: 002-04715 Rev. *C Page 38 of 76
CY96F6A6R
• Sample recommended circuits:
*5: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal
conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = Σ (VOL IOL + VOH IOH) (I/O load power dissipation, sum is performed on all I/O ports)
PINT = VCC (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in the “DC characteristics” and depends on the selected
operation mode and clock frequency and the usage of functions like Flash programming.
IA is the analog current consumption into AVCC.
*6: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
WARNING
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
VCC
R
+B input (0V to 16V)
Limiting
resistance
Protective diode
P-ch
N-ch
A yCYPRESS CY96F6A6R (Vss = AVss = DVss = 0V) Value Mm Typ Max cc
Document Number: 002-04715 Rev. *C Page 39 of 76
CY96F6A6R
14.2 Recommended Operating Conditions (VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
Power supply voltage
VCC,
AVCC,
DVCC
2.7
-
5.5
V
2.0
-
5.5
V
Maintains RAM data in stop mode
Smoothing capacitor at
C pin
CS
0.5
1.0 to 3.9
4.7
F
1.0F (Allowance within ± 50%)
3.9µF (Allowance within ± 20%)
Please use the ceramic capacitor or the capacitor
of the frequency response of this level.
The smoothing capacitor at VCC must use the one
of a capacity value that is larger than CS.
WARNING
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
:iCYPRESS' CY96F6A6R ' EMaEnnEnmmMaunw Fin Value Min Typ Max
Document Number: 002-04715 Rev. *C Page 40 of 76
CY96F6A6R
14.3 DC Characteristics
14.3.1 Current Rating (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Power supply
current in Run
modes*1
ICCPLL
Vcc
PLL Run mode with CLKS1/2 = CLKB
= CLKP1/2 = 32MHz
Flash 0 wait
(CLKRC and CLKSC stopped)
-
28
-
mA
TA = +25°C
-
-
38
mA
TA = +105°C
ICCMAIN
Main Run mode with CLKS1/2 =
CLKB = CLKP1/2 = 4MHz
Flash 0 wait
(CLKPLL, CLKSC and CLKRC
stopped)
-
3.5
-
mA
TA = +25°C
-
-
8
mA
TA = +105°C
ICCRCH
RC Run mode with CLKS1/2 = CLKB
= CLKP1/2 = CLKRC = 2MHz
Flash 0 wait
(CLKMC, CLKPLL and CLKSC
stopped)
-
1.8
-
mA
TA = +25°C
-
-
6
mA
TA = +105°C
ICCRCL
RC Run mode with CLKS1/2 = CLKB
= CLKP1/2 = CLKRC = 100kHz
Flash 0 wait
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.16
-
mA
TA = +25°C
-
-
3.5
mA
TA = +105°C
ICCSUB
Sub Run mode with CLKS1/2 = CLKB
= CLKP1/2 = 32kHz
Flash 0 wait
(CLKMC, CLKPLL and CLKRC
stopped)
-
0.1
-
mA
TA = +25°C
-
-
3.3
mA
TA = +105°C
A 2‘ CYPRESS’ Enasunsn m rowunw' CY96F6A6R Pin Value Mm Typ Max
Document Number: 002-04715 Rev. *C Page 41 of 76
CY96F6A6R
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Power supply
current in Sleep
modes*1
ICCSPLL
Vcc
PLL Sleep mode with
CLKS1/2 = CLKP1/2 = 32MHz
(CLKRC and CLKSC stopped)
-
9.5
-
mA
TA = +25°C
-
-
15
mA
TA = +105°C
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2 = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and CLKSC
stopped)
-
1.1
-
mA
TA = +25°C
-
-
4.7
mA
TA = +105°C
ICCSRCH
RC Sleep mode with CLKS1/2
= CLKP1/2 = CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.6
-
mA
TA = +25°C
-
-
4.1
mA
TA = +105°C
ICCSRCL
RC Sleep mode with CLKS1/2
= CLKP1/2 = CLKRC = 100kHz
(CLKMC, CLKPLL and CLKSC
stopped)
-
0.07
-
mA
TA = +25°C
-
-
2.9
mA
TA = +105°C
ICCSSUB
Sub Sleep mode with
CLKS1/2 = CLKP1/2 = 32kHz,
(CLKMC, CLKPLL and CLKRC
stopped)
-
0.04
-
mA
TA = +25°C
-
-
2.7
mA
TA = +105°C
Power supply
current in Timer
modes*2
ICCTPLL
PLL Timer mode with CLKPLL
= 32MHz (CLKRC and CLKSC
stopped)
-
1800
2250
A
TA = +25°C
-
-
3220
A
TA = +105°C
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKRC and CLKSC
stopped)
-
285
330
A
TA = +25°C
-
-
1200
A
TA = +105°C
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKPLL, CLKMC and CLKSC
stopped)
-
160
215
A
TA = +25°C
-
-
1110
A
TA = +105°C
ICCTRCL
RC Timer mode with
CLKRC = 100kHz
(CLKPLL, CLKMC and CLKSC
stopped)
-
35
75
A
TA = +25°C
-
-
910
A
TA = +105°C
ICCTSUB
Sub Timer mode with
CLKSC = 32kHz
(CLKMC, CLKPLL and CLKRC
stopped)
-
25
65
A
TA = +25°C
-
-
885
A
TA = +105°C
:iCYPRESS' CY96F6A6R ' EMaEnnEnmmMaunw'
Document Number: 002-04715 Rev. *C Page 42 of 76
CY96F6A6R
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Power supply current in
Stop mode*3
ICCH
Vcc
-
-
20
60
A
TA = +25°C
-
-
880
A
TA = +105°C
Flash Power Down
current
ICCFLASHPD
-
-
36
70
A
Power supply current
for active Low
Voltage detector*4
ICCLVD
Low voltage detector
enabled
-
5
-
A
TA = +25°C
-
-
12.5
A
TA = +105°C
Flash Write/
Erase current*5
ICCFLASH
-
-
12.5
-
mA
TA = +25°C
-
-
20
mA
TA = +105°C
*1: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and
a 32kHz external clock connected to the Sub oscillator. See chapter “Standby mode and voltage regulator control circuit” of the
Hardware Manual for further details about voltage regulator control. Current for "On Chip Debugger" part is not included. Power
supply current in Run mode does not include Flash Write / Erase current.
*2: The power supply current in Timer mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. The current for "On Chip Debugger" part is not included.
*3: The power supply current in Stop mode is the value when Flash is in Power-down / reset mode.
When Flash is not in Power-down / reset mode, ICCFLASHPD must be added to the Power supply current.
*4: When low voltage detector is enabled, ICCLVD must be added to Power supply current.
*5: When Flash Write / Erase program is executed, ICCFLASH must be added to Power supply current.
{EMPRESS CY96F6A6R z .sunsnwmmw Value Min Typ Max
Document Number: 002-04715 Rev. *C Page 43 of 76
CY96F6A6R
14.3.2 Pin Characteristics (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
"H" level input
voltage
VIH
Port inputs
Pnn_m
-
VCC
0.7
-
VCC
+ 0.3
V
CMOS Hysteresis input
-
VCC
0.8
-
VCC
+ 0.3
V
AUTOMOTIVE
Hysteresis input
VIHX0S
X0
External clock in
"Fast Clock Input mode"
VD
0.8
-
VD
V
VD=1.8V±0.15V
VIHX0AS
X0A
External clock in
"Oscillation mode"
VCC
0.8
-
VCC
+ 0.3
V
VIHR
RSTX
-
VCC
0.8
-
VCC
+ 0.3
V
CMOS Hysteresis input
VIHM
MD
-
VCC
- 0.3
-
VCC
+ 0.3
V
CMOS Hysteresis input
VIHD
DEBUG I/F
-
2.0
-
VCC
+ 0.3
V
TTL Input
"L" level input
voltage
VIL
Port inputs
Pnn_m
-
VSS
- 0.3
-
VCC
0.3
V
CMOS Hysteresis input
-
VSS
- 0.3
-
VCC
0.5
V
AUTOMOTIVE
Hysteresis input
VILX0S
X0
External clock in "Fast Clock
Input mode"
VSS
-
VD
0.2
V
VD=1.8V±0.15V
VILX0AS
X0A
External clock in
"Oscillation mode"
VSS
- 0.3
-
VCC
0.2
V
VILR
RSTX
-
VSS
- 0.3
-
VCC
0.2
V
CMOS Hysteresis input
VILM
MD
-
VSS
- 0.3
-
VSS
+ 0.3
V
CMOS Hysteresis input
VILD
DEBUG I/F
-
VSS
- 0.3
-
0.8
V
TTL Input
CYPRESS’ Enasunsn m mamw» Value Typ Max 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H 0H m m m m m m m m m m m CY96F6A6R
Document Number: 002-04715 Rev. *C Page 44 of 76
CY96F6A6R
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
"H" level
output voltage
VOH4
4mA type
4.5V ≤ (D)VCC ≤ 5.5V
IOH = -4mA
(D)VCC
- 0.5
-
(D)VCC
V
2.7V ≤ (D)VCC < 4.5V
IOH = -1.5mA
VOH30
High Drive
type*
4.5V ≤ DVCC ≤ 5.5V
IOH = -52mA
DVCC
- 0.5
-
DVCC
V
TA = -40°C
2.7V ≤ DVCC < 4.5V
IOH = -18mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -39mA
TA = +25°C
2.7V ≤ DVCC < 4.5V
IOH = -16mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -32mA
TA = +85°C
2.7V ≤ DVCC < 4.5V
IOH = -14.5mA
4.5V ≤ DVCC ≤ 5.5V
IOH = -30mA
TA = +105°C
2.7V ≤ DVCC < 4.5V
IOH = -14mA
VOH3
3mA type
4.5V ≤ VCC ≤ 5.5V
IOH = -3mA
VCC
- 0.5
-
VCC
V
2.7V ≤ VCC < 4.5V
IOH = -1.5mA
"L" level
output voltage
VOL4
4mA type
4.5V ≤ (D)VCC ≤ 5.5V
IOL = +4mA
-
-
0.4
V
2.7V ≤ (D)VCC < 4.5V
IOL = +1.7mA
VOL30
High Drive
type*
4.5V ≤ DVCC ≤ 5.5V
IOL = +52mA
-
-
0.5
V
TA = -40°C
2.7V ≤ DVCC < 4.5V
IOL = +22mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +39mA
TA = +25°C
2.7V ≤ DVCC < 4.5V
IOL = +18mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +32mA
TA = +85°C
2.7V ≤ DVCC < 4.5V
IOL = +14mA
4.5V ≤ DVCC ≤ 5.5V
IOL = +30mA
TA = +105°C
2.7V ≤ DVCC < 4.5V
IOL = +13.5mA
VOL3
3mA type
2.7V ≤ VCC < 5.5V
IOL = +3mA
-
-
0.4
V
VOLD
DEBUG I/F
VCC = 2.7V
IOL = +25mA
0
-
0.25
V
:iCYPRESS' CY96F6A6R Enasnnsn m anunw’ Value Mm Typ Max
Document Number: 002-04715 Rev. *C Page 45 of 76
CY96F6A6R
Parameter
Symbol
Pin Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Input leak
current
IIL
Pnn_m
VSS < VI < VCC
AVSS, AVRL < VI < AVCC, AVRH
- 1
-
+ 1
A
Single port pin
except high current
output I/O for SMC
P08_m,
P09_m,
P10_m
DVSS < VI < DVCC
AVSS, AVRL < VI < AVCC, AVRH
- 3
-
+ 3
A
Total LCD leak
current
Σ|IILCD|
All SEG/
COM pin
VCC = 5.0V
-
0.5
10
A
Maximum leakage
current of all LCD pins
Internal LCD
divide
resistance
RLCD
Between
V3 and V2,
V2 and V1,
V1 and V0
VCC = 5.0V
6.25
12.5
25
k
Pull-up
resistance
value
RPU
Pnn_m
VCC = 5.0V ±10%
25
50
100
k
Pull-down
resistance
value
RDOWN
P08_m,
P09_m,
P10_m
VCC = 5.0V ±10%
25
50
100
k
Input
capacitance
CIN
Other than C,
Vcc,
Vss,
DVcc,
DVss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
-
-
5
15
pF
P08_m,
P09_m,
P10_m
-
-
15
30
pF
*: In the case of driving stepping motor directly or high current outputs, set "1" to the bit in the Port High Drive Register
(PHDRnn:HDx="1").
CYPRESS‘ CY96F6A6R smasnnsn m anunw’ Fin When using me crystal oscillator ‘cvui 4—» Reference value: X09“ 1.8V10.15V The amplitude changes by resislanoe, mpacily which added outside or the difference of the device When using the external clock X0
Document Number: 002-04715 Rev. *C Page 46 of 76
CY96F6A6R
14.4 AC Characteristics
14.4.1 Main Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VD=1.8V±0.15V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Name
Value
Unit
Remarks
Min
Typ
Max
Input frequency
fC
X0,
X1
4
-
8
MHz
When using a crystal oscillator,
PLL off
-
-
8
MHz
When using an opposite phase
external
clock, PLL off
4
-
8
MHz
When using a crystal oscillator
or opposite
phase external clock, PLL on
Input frequency
fFCI
X0
-
-
8
MHz
When using a single phase
external
clock in “Fast Clock Input
mode”, PLL off
4
-
8
MHz
When using a single phase
external
clock in “Fast Clock Input
mode”, PLL on
Input clock cycle
tCYLH
-
125
-
-
ns
Input clock pulse width
PWH,
PWL
-
55
-
-
ns
QCYPRESS' CY96F6A6R ' EMaEnnEnmmMaunw Pin When using the crystal oscillakIr XOA,X1A When using the external clock XOA
Document Number: 002-04715 Rev. *C Page 47 of 76
CY96F6A6R
14.4.2 Sub Clock Input Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Input frequency
fCL
X0A,
X1A
-
-
32.768
-
kHz
When using an oscillation
circuit
-
-
-
100
kHz
When using an opposite
phase external clock
X0A
-
-
-
50
kHz
When using a single
phase external clock
Input clock cycle
tCYLL
-
-
10
-
-
s
Input clock pulse width
-
-
PWH/tCYLL,
PWL/tCYLL
30
-
70
%
fiCYPREss CY96F6A6R z .snnsnwmmw
Document Number: 002-04715 Rev. *C Page 48 of 76
CY96F6A6R
14.4.3 Built-in RC Oscillation Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
Clock frequency
fRC
50
100
200
kHz
When using slow frequency of RC
oscillator
1
2
4
MHz
When using fast frequency of RC
oscillator
RC clock stabilization time
tRCSTAB
80
160
320
s
When using slow frequency of RC
oscillator
(16 RC clock cycles)
64
128
256
s
When using fast frequency of RC
oscillator
(256 RC clock cycles)
14.4.4 Internal Clock Timing (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Min
Max
Internal System clock frequency
(CLKS1 and CLKS2)
fCLKS1, fCLKS2
-
54
MHz
Internal CPU clock frequency (CLKB),
Internal peripheral clock frequency (CLKP1)
fCLKB, fCLKP1
-
32
MHz
Internal peripheral clock frequency (CLKP2)
fCLKP2
-
32
MHz
ficvanss CY96F6A6R ' EHaEunEniumwunw Deviation time from the ideal clock is assured per cycle on! of 20,000 cycles, PLL°“'P“‘|—| l_|!|l_|| I I.“ I I'2 . (3 ”ill-I I: In : w..* a .* w. .* if $..+ [GI-”lock . .. . . . . .. .: SI | | : 0W : : : : ' i i Deviafion I E 5 t1 : ‘2 iime l 2 m Fast
Document Number: 002-04715 Rev. *C Page 49 of 76
CY96F6A6R
14.4.5 Operating Conditions of PLL (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Value
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time
tLOCK
1
-
4
ms
For CLKMC = 4MHz
PLL input clock frequency
fPLLI
4
-
8
MHz
PLL oscillation clock frequency
fCLKVCO
56
-
108
MHz
Permitted VCO output frequency
of PLL (CLKVCO)
PLL phase jitter
tPSKEW
-5
-
+5
ns
For CLKMC (PLL input clock) ≥
4MHz
14.4.6 Reset Input (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin Name
Value
Unit
Min
Max
Reset input time
tRSTL
RSTX
10
-
s
Rejection of reset input time
1
-
s
RSTX
0.2VCC 0.2VCC
tRSTL
:iCYPRESS' CY96F6A6R ' EMaEnnEnmmMaunw If the power supply is changed too rapidly, a power-on reset my occur, We recommend a smooth startup by restrairl'ng voltages when changing the power supply voltage during operation, as shown in the figue below. It is reun that rises in votbge have a slope of 50 mVIms or less.
Document Number: 002-04715 Rev. *C Page 50 of 76
CY96F6A6R
14.4.7 Power-on Reset Timing (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin Name
Value
Unit
Min
Typ
Max
Power on rise time
tR
Vcc
0.05
-
30
ms
Power off time
tOFF
Vcc
1
-
-
ms
EMPRESS CY96F6A6R Enasnnsn m anunw’
Document Number: 002-04715 Rev. *C Page 51 of 76
CY96F6A6R
14.4.8 USART Timing
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C, CL=50pF)
Parameter
Symbo
l
Pin
Name
Conditions
4.5V VCC 5.5V
2.7V VCC 4.5V
Uni
t
Min
Max
Min
Max
Serial clock cycle time
tSCYC
SCKn
Internal shift
clock mode
4tCLKP1
-
4tCLKP1
-
ns
SCK SOT delay time
tSLOVI
SCKn,
SOTn
- 20
+ 20
- 30
+ 30
ns
SOT SCK delay time
tOVSHI
SCKn,
SOTn
NtCLKP1
– 20*
-
NtCLKP1
– 30*
-
ns
SIN SCK setup time
tIVSHI
SCKn,
SINn
tCLKP1
+ 45
-
tCLKP1
+ 55
-
ns
SCK SIN hold time
tSHIXI
SCKn,
SINn
0
-
0
-
ns
Serial clock "L" pulse width
tSLSH
SCKn
External shift
clock mode
tCLKP1
+ 10
-
tCLKP1
+ 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKn
tCLKP1
+ 10
-
tCLKP1
+ 10
-
ns
SCK SOT delay time
tSLOVE
SCKn,
SOTn
-
2tCLKP1
+ 45
-
2tCLKP1
+ 55
ns
SIN SCK setup time
tIVSHE
SCKn,
SINn
tCLKP1/2
+ 10
-
tCLKP1/2
+ 10
-
ns
SCK SIN hold time
tSHIXE
SCKn,
SINn
tCLKP1
+ 10
-
tCLKP1
+ 10
-
ns
SCK fall time
tF
SCKn
-
20
-
20
ns
SCK rise time
tR
SCKn
-
20
-
20
ns
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “CY96600 series HARDWARE MANUAL”.
• tCLKP1 indicates the peripheral clock 1 (CLKP1), Unit: ns
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCKn and SOTn_R is not guaranteed.
*: Parameter N depends on tSCYC and can be calculated as follows:
• If tSCYC = 2 ktCLKP1, then N = k, where k is an integer > 2
• If tSCYC = (2 k + 1) tCLKP1, then N = k + 1, where k is an integer > 1
Examples:
tSCYC
N
4 tCLKP1
2
5 tCLKP1, 6 tCLKP1
3
7 tCLKP1, 8 tCLKP1
4
...
...
*CYPRESS‘ CY96F6A6R msnnsnumumnw-
Document Number: 002-04715 Rev. *C Page 52 of 76
CY96F6A6R
tSCYC
VOL VOL
VOH
VOH
VIH VIH
VIL
VIL
tSLOVI
tIVSHI tSHIXI
VOL
SCK
SOT
SIN
Internal shift clock mode
tOVSHI
tSLSH VIH VIH
VIH
VIH
VIL
VIH
VIL
VIL VIL
VOL
VOH
tSLOVE
tR
tSHIXE
tIVSHE
tF
SCK
SOT
SIN
tSHSL
External shift clock mode
acvpkEss CY96F6A6R ' EMaEnnEnmmMaunw'
Document Number: 002-04715 Rev. *C Page 53 of 76
CY96F6A6R
14.4.9 External Input Timing (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin Name
Value
Unit
Remarks
Min
Max
Input pulse width
tINH,
tINL
Pnn_m
2tCLKP1 +200
(tCLKP1=
1/fCLKP1)*
-
ns
General Purpose I/O
ADTG
A/D Converter trigger input
TINn, TINn_R
Reload Timer
TTGn
PPG trigger input
FRCKn,
FRCKn_R
Free-Running Timer input clock
INn, INn_R
Input Capture
INTn, INTn_R
200
-
ns
External Interrupt
NMI
Non-Maskable Interrupt
*: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time except stop when in stop mode.
VIH VIL
tINL
tINH
VIL
External input timing VIH
ficvanss CY96F6A6R nnnnnnnnnnnnnnnnnnn [Low ‘
Document Number: 002-04715 Rev. *C Page 54 of 76
CY96F6A6R
14.4.10 I2C Timing (VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Typical Mode
High-Speed Mode*4
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
CL = 50pF,
R = (Vp/IOL)*1
0
100
0
400
kHz
(Repeated) START condition hold time
SDA SCL
tHDSTA
4.0
-
0.6
-
s
SCL clock "L" width
tLOW
4.7
-
1.3
-
s
SCL clock "H" width
tHIGH
4.0
-
0.6
-
s
(Repeated) START condition setup time
SCL SDA
tSUSTA
4.7
-
0.6
-
s
Data hold time
SCL SDA
tHDDAT
0
3.45*2
0
0.9*3
s
Data setup time
SDA SCL
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL SDA
tSUSTO
4.0
-
0.6
-
s
Bus free time between
"STOP condition" and
"START condition"
tBUS
4.7
-
1.3
-
s
Pulse width of spikes which will be
suppressed by input noise filter
tSP
-
0
(1-1.5)
tCLKP1*5
0
(1-1.5)
tCLKP1*5
ns
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT only has to be met if the device does not extend the "L" width (tLOW) of the SCL signal.
*3: A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250ns".
*4: For use at over 100kHz, set the peripheral clock1 (CLKP1) to at least 6MHz.
*5: tCLKP1 indicates the peripheral clock1 (CLKP1) cycle time.
SDA
SCL
tHDSTA
tLOW
tHDDAT
tSUDAT
tHIGH
tSUSTA
tHDSTA tSP
tBUS
tSUSTO
EMPRESS CY96F6A6R Enasunsn m rowunw'
Document Number: 002-04715 Rev. *C Page 55 of 76
CY96F6A6R
14.5 A/D Converter
14.5.1 Electrical Characteristics for the A/D Converter
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Name
Value
Unit
Remarks
Min
Typ
Max
Resolution
-
-
-
-
10
bit
Total error
-
-
- 3.0
-
+ 3.0
LSB
Nonlinearity error
-
-
- 2.5
-
+ 2.5
LSB
Differential
Nonlinearity error
-
-
- 1.9
-
+ 1.9
LSB
Zero transition
voltage
VOT
ANn
Typ - 20
AVRL
+ 0.5LSB
Typ + 20
mV
Full scale transition
voltage
VFST
ANn
Typ - 20
AVRH
- 1.5LSB
Typ + 20
mV
Compare time*
-
-
1.0
-
5.0
s
4.5V ≤ ΑVCC ≤ 5.5V
2.2
-
8.0
s
2.7V ≤ ΑVCC 4.5V
Sampling time*
-
-
0.5
-
-
s
4.5V ≤ ΑVCC ≤ 5.5V
1.2
-
-
s
2.7V ≤ ΑVCC 4.5V
Power supply current
IA
AVCC
-
2.0
3.1
mA
A/D Converter active
IAH
-
-
3.3
A
A/D Converter not
operated
Reference power
supply current
(between AVRH and
AVRL)
IR
AVRH
-
520
810
A
A/D Converter active
IRH
-
-
1.0
A
A/D Converter not
operated
Analog input capacity
CVIN
AN0 to 15
-
-
16.0
pF
Normal outputs
AN16 to 31
-
-
17.8
pF
High current outputs
Analog impedance
RVIN
ANn
-
-
2050
4.5V ≤ AVCC ≤ 5.5V
-
-
3600
2.7V ≤ AVCC < 4.5V
Analog port input
current (during
conversion)
IAIN
AN0 to 15
- 0.3
-
+ 0.3
A
AVSS , AVRL VAIN
AVCC, AVRH
AN16 to 31
- 3.0
-
+ 3.0
A
Analog input voltage
VAIN
ANn
AVRL
-
AVRH
V
Reference voltage
range
-
AVRH
AVCC
- 0.1
-
AVCC
V
-
AVRL
AVSS
-
AVSS
+ 0.1
V
Variation between
channels
-
ANn
-
-
4.0
LSB
*: Time for each channel.
Document Number: 002-04715 Rev. *C Page 56 of 76
CY96F6A6R
14.5.2 Accuracy and Setting of the A/D Converter Sampling Time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold
capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time (Tsamp) depends
on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and the AVCC voltage level. The
following replacement model can be used for the calculation:
Rext: External driving impedance
Cext: Capacitance of PCB at A/D converter input
CVIN: Analog input capacity (I/O, analog switch and ADC are contained)
RVIN: Analog input impedance (I/O, analog switch and ADC are contained)
The following approximation formula for the replacement model above can be used:
Tsamp = 7.62 (Rext Cext + (Rext + RVIN) CVIN)
Do not select a sampling time below the absolute minimum permitted value.
(0.5s for 4.5V ≤ AVCC ≤ 5.5V, 1.2s for 2.7V ≤ AVCC < 4.5V)
If the sampling time cannot be sufficient, connect a capacitor of about 0.1F to the analog input pin.
A big external driving impedance also adversely affects the A/D conversion precision due to the pin input leakage current IIL
(static current before the sampling switch) or the analog input leakage current IAIN (total leakage current of pin input and
comparator during sampling). The effect of the pin input leakage current IIL cannot be compensated by an external capacitor.
The accuracy gets worse as |AVRH - AVRL| becomes smaller.
Sampling switch
(During sampling:ON)
CVIN
RVIN
Analog
input
MCU
Rext
Cext
Source Comparator
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Document Number: 002-04715 Rev. *C Page 57 of 76
CY96F6A6R
14.5.3 Definition of A/D Converter Terms
Resolution : Analog variation that is recognized by an A/D converter.
Nonlinearity error : Deviation of the actual conversion characteristics from a straight line that connects the zero transition
point (0b0000000000 ←→ 0b0000000001) to the full-scale transition point (0b1111111110 ←→
0b1111111111).
Differential nonlinearity error : Deviation from the ideal value of the input voltage that is required to change the output code by
1LSB.
Total error : Difference between the actual value and the theoretical value. The total error includes zero transition
error, full-scale transition error and nonlinearity error.
Zero transition voltage: Input voltage which results in the minimum conversion value.
Full scale transition voltage: Input voltage which results in the maximum conversion value.
Nonlinearity error of digital output N =
VNT - {1LSB (N - 1) + VOT}
[LSB]
1LSB
Differential nonlinearity error of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
1LSB =
VFST - VOT
1022
N : A/D converter digital output value.
VOT : Voltage at which the digital output changes from 0x000 to 0x001.
VFST : Voltage at which the digital output changes from 0x3FE to 0x3FF.
VNT : Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:iCYPRESS' CY96F6A6R ' mmsnumumnw- Total error 0x3FF’ {7 3 1.5 LSB oxaFE ‘ ‘7 0x3FD7 ‘, 3 ‘5 3 a. ‘5 o T! 0x004 7 ‘ ‘ E! 1 3 m D “003’ 3 """" ‘ (Annually—mama: value) 3 vi Mual Ixmvers'ml 0‘002’ ; , chalader'stics ‘ ‘—?*ldeal dualacterBtEs 0x001 7 ‘ 77777 7‘ Ives LSB AVRL AVRH Analog irput
Document Number: 002-04715 Rev. *C Page 58 of 76
CY96F6A6R
1LSB (Ideal value) =
AVRH - AVRL
[V]
1024
Total error of digital output N =
VNT - {1LSB (N - 1) + 0.5LSB}
1LSB
N : A/D converter digital output value.
VNT : Voltage at which the digital output changes from 0x(N + 1) to 0xN.
VOT (Ideal value) = AVRL + 0.5LSB[V]
VFST (Ideal value) = AVRH - 1.5LSB[V]
ficvanss CY96F6A6R ' sM-snnsnumumw Pin Value Min Typ Max
Document Number: 002-04715 Rev. *C Page 59 of 76
CY96F6A6R
14.6 High Current Output Slew Rate
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Pin
Name
Conditions
Value
Unit
Remarks
Min
Typ
Max
Output rise/fall time
tR30,
tF30
P08_m,
P09_m,
P10_m
Outputs
driving
strength set to
"30mA"
15
-
75
ns
CL=85pF
VHVH
Voltage
Time
VLVL
VH=VOL30+0.9 × (VOH30-VOL30)
VL=VOL30+0.1 × (VOH30-VOL30)
tR30 tF30
:iCYPRESS' CY96F6A6R ' EMaEnnEnmmwunw
Document Number: 002-04715 Rev. *C Page 60 of 76
CY96F6A6R
14.7 Low Voltage Detection Function Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Symbol
Conditions
Value
Unit
Min
Typ
Max
Detected voltage*1
VDL0
CILCR:LVL = 0000B
2.70
2.90
3.10
V
VDL1
CILCR:LVL = 0001B
2.79
3.00
3.21
V
VDL2
CILCR:LVL = 0010B
2.98
3.20
3.42
V
VDL3
CILCR:LVL = 0011B
3.26
3.50
3.74
V
VDL4
CILCR:LVL = 0100B
3.45
3.70
3.95
V
VDL5
CILCR:LVL = 0111B
3.73
4.00
4.27
V
VDL6
CILCR:LVL = 1001B
3.91
4.20
4.49
V
Power supply voltage change
rate*2
dV/dt
-
- 0.004
-
+ 0.004
V/s
Hysteresis width
VHYS
CILCR:LVHYS=0
-
-
50
mV
CILCR:LVHYS=1
80
100
120
mV
Stabilization time
TLVDSTAB
-
-
-
75
s
Detection delay time
td
-
-
-
30
s
*1: If the power supply voltage fluctuates within the time less than the detection delay time (td), there is a possibility that the low
voltage detection will occur or stop after the power supply voltage passes the detection range.
*2: In order to perform the low voltage detection at the detection voltage (VDLX), be sure to suppress fluctuation of the power
supply voltage within the limits of the change ration of power supply voltage.
A yCYPRESS CY96F6A6R A Volhge A Inierml Resei ’/ Vcc Release Voltage adv id 1 mi Normal Operafion >
Document Number: 002-04715 Rev. *C Page 61 of 76
CY96F6A6R
Time
Vcc
VDLX min
Voltage
VDLX max
dV
dt
Detected Voltage
RCR:LVDE
···Low voltage detection
function enable Low voltage detection
function disable Stabilization time
TLVDSTAB
Low voltage detection
function enable···
:iCYPRESS' EMaEnnEn m mamw» Write/Erase Cycles Dale Hold Time CY96F6A6R
Document Number: 002-04715 Rev. *C Page 62 of 76
CY96F6A6R
14.8 Flash Memory Write/Erase Characteristics
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = - 40°C to + 105°C)
Parameter
Conditions
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
Large Sector
-
-
1.6
7.5
s
Includes write time prior to
internal erase.
Small Sector
-
-
0.4
2.1
s
Security Sector
-
-
0.31
1.65
s
Word (16-bit) write time
-
-
25
400
s
Not including system-level
overhead
time.
Chip erase time
-
-
8.31
40.05
s
Includes write time prior to
internal erase.
Note: While the Flash memory is written or erased, shutdown of the external power (VCC) is prohibited. In the application system
where the external power (VCC) might be shut down while writing or erasing, be sure to turn the power off by using a low
voltage detection function.
To put it concrete, change the external power in the range of change ration of power supply voltage (-0.004V/s to
+0.004V/s) after the external power falls below the detection voltage (VDLX)*1.
Write/Erase cycles and data hold time
Write/Erase Cycles
(Cycle)
Data Hold Time
(Year)
1,000
20 *2
10,000
10 *2
100,000
5 *2
*1: See "14.7. Low Voltage Detection Function Characteristics".
*2: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements
into normalized value at + 85C).
CY96F6A6R \
Document Number: 002-04715 Rev. *C Page 63 of 76
CY96F6A6R
15. Example Characteristics
This characteristic is an actual value of the arbitrary sample. It is not the guaranteed value.
CY96F6A6
0.01
0.10
1.00
10.00
100.00
-50 0 50 100 150
ICC [mA]
TA[ºC]
Run Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(VCC = 5.5V)
RC clock (2MHz)
0.001
0.010
0.100
1.000
10.000
100.000
-50 0 50 100 150
ICC [mA]
TA[ºC]
Sleep Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(VCC = 5.5V)
A yCYPRESS CY96F6A6R ICY96F6A6 ll
Document Number: 002-04715 Rev. *C Page 64 of 76
CY96F6A6R
CY96F6A6
0.001
0.010
0.100
1.000
10.000
-50 0 50 100 150
ICC [mA]
TA[ºC]
Timer Mode
PLL clock (32MHz)
Main osc. (4MHz)
RC clock (2MHz)
RC clock (100kHz)
Sub osc. (32kHz)
(VCC = 5.5V)
0.001
0.010
0.100
1.000
-50 0 50 100 150
ICC [mA]
TA[ºC]
Stop Mode(VCC = 5.5V)
:iCYPRESS' CY96F6A6R Enasnnsn m anunw’ Selected Source Clock
Document Number: 002-04715 Rev. *C Page 65 of 76
CY96F6A6R
Used setting
Mode
Selected Source
Clock
Clock/Regulator and FLASH Settings
Run mode
PLL
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32MHz
Main osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 4MHz
RC clock fast
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 2MHz
RC clock slow
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 100kHz
Sub osc.
CLKS1 = CLKS2 = CLKB = CLKP1 = CLKP2 = 32kHz
Sleep mode
PLL
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
Main osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 4MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock fast
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 2MHz
Regulator in High Power Mode,
(CLKB is stopped in this mode)
RC clock slow
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 100kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Sub osc.
CLKS1 = CLKS2 = CLKP1 = CLKP2 = 32kHz
Regulator in Low Power Mode,
(CLKB is stopped in this mode)
Timer mode
PLL
CLKMC = 4MHz, CLKPLL = 32MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
Main osc.
CLKMC = 4MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock fast
CLKMC = 2MHz
(System clocks are stopped in this mode)
Regulator in High Power Mode,
FLASH in Power-down / reset mode
RC clock slow
CLKMC = 100kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Sub osc.
CLKMC = 32 kHz
(System clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
Stop mode
stopped
(All clocks are stopped in this mode)
Regulator in Low Power Mode,
FLASH in Power-down / reset mode
ficvpkEss CY96F6A6R ' EMIinnEnlumuunw'
Document Number: 002-04715 Rev. *C Page 66 of 76
CY96F6A6R
16. Ordering Information
MCU with CAN Controller
Part Number
Flash Memory
Package*
CY96F6A6RBPMC-GS-UJE1
Flash A
(288.5KB)
120-pin plastic LQFP
(LQM120)
CY96F6A6RBPMC-GS-UJE2
CY96F6A6RBPMC-GS-UJERE2
120-pin Reel LQFP
(LQM120)
*: For details about package, see "Package Dimension".
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Document Number: 002-04715 Rev. *C Page 67 of 76
CY96F6A6R
17. Package Dimension
M IN. NOM . M AX.
07.1A
A1 0.05 0.15
b 0.17 0.22 0.27
c0.115 0.195
D 18.00 BSC
D1 16.00 BSC
e0.50 BSC
E
E1
L 0.45 0.60 0.75
18.00 BSC
16.00 BSC
DIM ENSIONS
SYM BOL
θ0°8°
SIDE VIEW
BOTTOM VIEW
TOP VIEW
1
120
D1
D
e
EE1
0.20 C A -B D
0.10 C A -B D
0.08 C A-B D
b
0.08 C
SEATI NG
PLA NE
A
A'
θ
A
A1
0.25 10
L
b
SEC TION A -A'
c
9
4
57
3
4
5
7
3
8
7
5
2
2
6
30
31
60
6190
91
130
31
60
0916
91
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18 .0X1.7 M MLQM120 REV**
002-16172 **
EMPRESS CY96F6A6R Enasunsn m rowunw'
Document Number: 002-04715 Rev. *C Page 68 of 76
CY96F6A6R
18. Major Changes
Spansion Publication Number: MB96F6A6-DS704-00010
Page
Section
Change Results
Revision 1.0
-
-
PRELIMINARY → Data sheet
2
Features
Changed the description of “System clock”
Up to 16 MHz external clock for devices with fast clock input feature
→
Up to 8 MHz external clock for devices with fast clock input feature
3
Changed the description of “Free-Running Timers”
Signals an interrupt on overflow
→
Signals an interrupt on overflow, supports timer clear upon match with
Output Compare (0, 4)
4
Changed the description of “LCD Controller”
On-chip drivers for internal divider resistors or external divider
resistors
→
Internal divider resistors or external divider resistors
Changed the description of “External Interrupts”
Interrupt mask and pending bit per channel
→
Interrupt mask bit per channel
5
Changed the description of “Built-in On Chip Debugger”
- Event sequencer: 2 levels
→
- Event sequencer: 2 levels + reset
6
Product Lineup
Added the Product
Changed the Remark of RLT
RLT 0/1/2/3/6 Only RLT6 can be used as PPG clock source
→
RLT 0 to 3/6
Changed number of the I/O Ports
96 (Dual clock mode)
98 (Single clock mode)
→
95 (Dual clock mode)
97 (Single clock mode)
7
Block Diagram
Deleted the block of RLT6 from PPG block
Changed the RLT block
4ch
→
0/1/2/3/6 5ch
9
Pin Description
Changed the Description of PPGn_B
Programmable Pulse Generator n output (8bit)
→
Programmable Pulse Generator n output (16bit/8bit)
13
Pin Circuit Type
Changed the I/O circuit type of Pin no.116
P
→
Q
15
I/O Circuit Type
Changed the figure of type B
Changed the Remarks of type B
(CMOS hysteresis input with input shutdown function,
IOL = 4mA, IOH = -4mA, Programmable pull-up resister)
→
(CMOS level output (IOL = 4mA, IOH = -4mA), Automotive input with
input shutdown function and programmable pull-up resistor)
16
Changed the figure of type G
19
Added the Type Q
21
Memory Map
Changed the START addresses of Boot-ROM
0F:E000H
→
0F:C000H
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Change Results
23
User ROM Memory Map For Flash Devices
Changed the annotation
Others (from DF:0200H to DF:1FFFH) are all mirror area of SAS-512B.
→
Others (from DF:0200H to DF:1FFFH) is mirror area of SAS-512B.
25
Interrupt Vector Table
Changed the Description of CALLV0 to CALLV7
Reserved
→
CALLV instruction
Changed the Description of RESET
Reserved
→
Reset vector
Changed the Description of INT9
Reserved
→
INT9 instruction
Changed the Description of EXCEPTION
Reserved
→
Undefined instruction execution
26
Changed the Vector name of Vector number 64
PPGRLT
→
RLT6
Changed the Description of Vector number 64
Reload Timer 6 can be used as PPG clock source
→
Reload Timer 6
29 to 32
Handling Precautions
Added a section
34
Handling Devices
Added the description to “3. External clock usage”
(3) Opposite phase external clock
Changed the description in “7. Turn on sequence of power supply to
A/D converter and analog inputs”
In this case, the voltage must not exceed AVRH or AVCC
→
In this case, AVRH must not exceed AVCC. Input voltage for ports
shared with analog input ports also must not exceed AVCC
35
Handling Devices
Changed the description in “11. SMC power supply pins”
To avoid this, VCC must always be powered on before DVCC.
→
To avoid this, VCC must always be powered on before DVCC.
DVcc/DVss must be applied when using SMC I/O pin as GPIO.
Added the description “13. Mode Pin (MD)”
36
Electrical Characteristics
Absolute Maximum Ratings
Changed the Symbol of “"L" level average overall output current”
ΣIOLSMCAV
→
ΣIOLAVSMC
Changed the Symbol of “"H" level average overall output current”
ΣIOHSMCAV
→
ΣIOHAVSMC
37
Changed the annotation *2
It is required that AVCC does not exceed VCC and that the voltage at
the analog inputs does not exceed AVCC when the power is switched
on.
→
It is required that AVCC does not exceed VCC, DVCC and that the
voltage at the analog inputs does not exceed AVCC when the power is
switched on.
Changed the annotation *3
Input/Output voltages of standard ports depend on VCC.
→
Input/Output voltages of high current ports depend on DVCC.
Input/Output voltages of standard ports depend on VCC.
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Changed the annotation *4
Note that if the +B input is applied during power-on, the power supply
is provided from the pins and the resulting supply voltage may not be
sufficient to operate the Power reset (except devices with persistent
low voltage reset in internal vector mode).
→
Note that if the +B input is applied during power-on, the power supply
is provided from the pins and the resulting supply voltage may not be
sufficient to operate the Power reset.
Added the annotation *4
The DEBUG I/F pin has only a protective diode against VSS. Hence it
is only permitted to input a negative clamping current (4mA). For
protection against positive input voltages, use an external clamping
diode which limits the input voltage to maximum 6.0V.
39
Recommended Operating Conditions
Added the Value and Remarks to “Power supply voltage”
Min: 2.0V
Typ: -
Max: 5.5V
Remarks: Maintains RAM data in stop mode
Changed the Value of “Smoothing capacitor at C pin”
Typ: 1.0F → 1.0F to 3.9F
Max: 1.5F → 4.7F
Changed the Remarks of “Smoothing capacitor at C pin”
Deleted “(Target value)”
Added “3.9F (Allowance within ± 20%)”
40
DC Characteristics
Current Rating
Deleted “(Target value)”
Added the Symbol to “Power supply current in Run modes”
ICCRCH, ICCRCL
Changed the Conditions of ICCPLL, ICCMAIN, ICCSUB in “Power supply
current in Run modes”
“Flash 0 wait” is added
Changed the Value of “Power supply current in Run modes”
ICCPLL
Typ: 28.5mA → 28mA (TA = +25°C)
ICCMAIN
Typ:5mA → 3.5mA (TA = +25°C)
Max: 10mA → 8mA (TA = +105°C)
ICCSUB
Typ:0.5mA → 0.1mA (TA = +25°C)
Max: 6mA → 3.3mA (TA = +105°C)
41
Added the Symbol to “Power supply current in Sleep modes”
ICCSRCH, ICCSRCL
Changed the Conditions of ICCSMAIN in “Power supply current in Sleep
modes”
“SMCR:LPMSS=0” is added
Changed the Value of “Power supply current in Sleep modes”
ICCSPLL
Typ:10mA → 9.5m A (TA = +25°C)
ICCSMAIN
Typ: 3mA → 1.1m A (TA = +25°C)
Max: 8mA → 4.7m A (TA = +105°C)
ICCSSUB
Typ: 0.3mA → 0.04m A (TA = +25°C)
Max: 4.5mA → 2.7m A (TA = +105°C)
Added the Symbol to “Power supply current in Timer modes”
ICCTPLL
Changed the Conditions of ICCTMAIN, ICCTRCH in “Power supply current in
Timer modes”
“SMCR:LPMSS=0” is added
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41
DC Characteristics
Current Rating
Changed the Value of “Power supply current in Timer modes”
ICCTMAIN
Max: 355A → 330A (TA = +25°C)
Max: 1320A→ 1200A (TA = +105°C)
ICCTRCH
Max: 245A → 215A (TA = +25°C)
Max: 1230A→ 1110A (TA = +105°C)
ICCTRCL
Max: 105A → 75A (TA = +25°C)
Max: 1030A → 910A (TA = +105°C)
ICCTSUB
Typ: 90A→ 65A (TA = +25°C)
Max: 1000A → 885A (TA = +105°C)
42
Changed the Value of “Power supply current in Stop modes”
ICCH
Max: 90A → 60A (TA = +25°C)
Max: 1000A → 880A (TA = +105°C)
Added the Symbol
ICCFLASHPD
Changed the Value and condition of “Power supply current for active
Low Voltage detector”
ICCLVD
Typ: 5A, Max: 15A, Remarks: nothing
→
Typ: 5A, Max: -, Remarks: TA = +25°C
Typ: -, Max: 12.5A, Remarks: TA = +105°C
Changed the condition of “Flash Write/Erase current”
ICCFLASH
Typ: 12.5mA, Max: 20mA, Remarks: nothing
→
Typ: 12.5mA, Max: -, Remarks: TA = +25°C
Typ: -, Max: 20mA, Remarks: TA = +105°C
Changed the annotation *2
The power supply current is measured with a 4MHz external clock
connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator.
→
The power supply current is measured with a 4MHz external clock
connected to the Main oscillator and a 32kHz external clock
connected to the Sub oscillator. The current for "On Chip Debugger"
part is not included.
44
DC Characteristics
Pin Characteristics
Added the Symbol for DEBUG I/F pin
VOLD
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45
DC Characteristics
Pin Characteristics
Changed the Pin name of “Input capacitance”
Other than
Vcc,
Vss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
→
Other than
C,
Vcc,
Vss,
DVcc,
DVss,
AVcc,
AVss,
AVRH,
AVRL,
P08_m,
P09_m,
P10_m
Deleted the annotation
“IOH and IOL are target value.”
Added the annotation
“In the case of driving stepping motor directly or high current outputs,
set "1" to the bit in the Port High Drive Register (PHDRnn:HDx="1").”
46
AC Characteristics
Main Clock Input Characteristics
Changed MAX frequency for fFCI in all conditions
16 → 8
Changed MIN frequency for tCYLH
62.5 → 125
Changed MIN, MAX and Unit for PWH, PWL
MIN: 30 → 55
MAX: 70 → -
Unit: % → ns
Added the figure (tCYLH) when using the external clock
47
AC Characteristics
Sub Clock Input Characteristics
Added the figure (tCYLL) when using the crystal oscillator clock
48
AC Characteristics
Built-in RC Oscillation Characteristics
Added “RC clock stabilization time”
49
AC Characteristics
Operating Conditions of PLL
Changed the Value of “PLL input clock frequency”
Max: 16MHz → 8MHz
Changed the Symbol of “PLL oscillation clock frequency”
fPLLO → fCLKVCO
Added Remarks to “PLL oscillation clock frequency”
Added “ PLL phase jitter” and the figure
AC Characteristics
Reset Input
Added the figure for reset input time (tRSTL)
51
AC Characteristics
USART Timing
Changed the condition
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = -
40°C to + 105°C)
→
(VCC = AVCC = DVCC = 2.7V to 5.5V, VSS = AVSS = DVSS = 0V, TA = -
40°C to + 105°C, CL = 50pF)
Changed the HARDWARE MANUAL
“MB966A0 series HARDWARE MANUAL”
→
“MB96600 series HARDWARE MANUAL”
52
Changed the figure for “Internal shift clock mode”
54
AC Characteristics
I2C timing
Added parameter, “Noise filter” and an annotation *5 for it
Added tSP to the figure
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55
A/D Converter
Electrical Characteristics for the A/D Converter
Added “Analog impedance”
Added “Variation between channels”
Added the annotation
56
A/D Converter
Accuracy and Setting of the A/D Converter
Sampling Time
Deleted the unit “[Min]” from approximation formula of Sampling time
57
A/D Converter
Definition of A/D Converter Terms
Changed the Description and the figure
“Linearity” → “Nonlinearity”
“Differential linearity error”
→
“Differential nonlinearity error”
Changed the Description
Linearity error:
Deviation of the line between the zero-transition point
(0b0000000000←→0b0000000001) and the full-scale transition point
(0b1111111110←→0b1111111111) from the actual conversion
characteristics.
→
Nonlinearity error:
Deviation of the actual conversion characteristics from a straight line
that connects the zero transition point (0b0000000000 ←→
0b0000000001) to the full-scale transition point (0b1111111110 ←→
0b1111111111).
Added the Description
“Zero transition voltage”
“Full scale transition voltage”
59
High Current Output Slew Rate
Changed the Symbol and figure
tR2, tF2, VOL2
→
tR30, tF30, VOL30
60
Low Voltage Detection Function Characteristics
Added the Value of “ Power supply voltage change rate”
Max: +0.004 V/s
Added “Hysteresis width” (VHYS)
Added “Stabilization time” (TLVDSTAB)
Added “Detection delay time” (td)
Deleted the Remarks
Added the annotation *1, *2
61
Added the figure for “Hysteresis width”
Added the figure for “Stabilization time”
62
Flash Memory Write/Erase Characteristics
Changed the Value of “Sector erase time”
Added “Security Sector” to “Sector erase time”
Changed the Parameter
“Half word (16 bit) write time”
→
“Word (16-bit) write time”
Changed the Value of “Chip erase time”
Changed the Remarks of “Sector erase time”
Excludes write time prior to internal erase
→
Includes write time prior to internal erase
Added the Note and annotation *1
Deleted “(targeted value)” from title “ Write/Erase cycles and data hold
time”
63 to 65
Example Characteristics
Added a section
66
Ordering information
Changed part number
MCU with CAN controller
MB96F6A6RAPMC-GSE1* → MB96F6A6RBPMC-GSE1
MB96F6A6RAPMC-GSE2* → MB96F6A6RBPMC-GSE2
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Added part number
MCU with CAN controller
MB96F6A5RBPMC-GSE1
MB96F6A5RBPMC-GSE2
MCU without CAN controller
MB96F6A5ABPMC-GSE1
MB96F6A5ABPMC-GSE2
Revision 1.1
-
-
Company name and layout design change
Rev. *B
-
Marketing Part Numbers changed from an MB prefix to a CY prefix.
5, 7,
66, 67
1. Product Lineup
3. Pin Assignment
16. Ordering Information
17. Package Dimension
Package description modified to JEDEC description.
FPT-120P-M21 → LQM120
66
16. Ordering Information
Revised Marketing Part Numbers as follows:
Before)
MCU with CAN controller
MB96F6A5RBPMC-GSE1
MB96F6A5RBPMC-GSE2
MB96F6A6RBPMC-GSE1
MB96F6A6RBPMC-GSE2
MCU without CAN controller
MB96F6A5ABPMC-GSE1
MB96F6A5ABPMC-GSE2
After)
MCU with CAN controller
CY96F6A6RBPMC-GS-UJE1
CY96F6A6RBPMC-GS-UJE2
CY96F6A6RBPMC-GS-UJERE2
NOTE: Please see “Document History” about later revised information.
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Document History
Document Title: CY96F6A6R, F2MC-16FX CY966A0 Series 16-bit Proprietary Microcontroller
Document Number: 002-04715
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
TORS
01/31/2014
Migrated to Cypress and assigned document number 002-4715.
No change to document contents or format.
*A
5166254
TORS
05/25/2016
Updated to Cypress template.
*B
6003420
MIYH
12/25/2017
Updated Document Title to read as
“CY96F6A5R/CY96F6A5A/CY96F6A6R, F2MC-16FX CY966A0
Series 16-bit Proprietary Microcontroller”.
Replaced MB966A0 Series with CY966A0 Series in all instances
across the document.
Changed the prefix of all MPNs from MB to CY in all instances across
the document.
Replaced FPT-120P-M21 with LQM120 in all instances across the
document.
Updated Ordering Information.
Updated to new template.
For details, please see 18. Major Changes.
*C
6601010
TORS
06/21/2019
Updated Document Title to read as “CY96F6A6R, F2MC-16FX
CY966A0 Series 16-bit Proprietary Microcontroller”.
Updated to new template.
Document Number: 002-04715 Rev. *C June 21, 2019 Page 76 of 76
CY96F6A6R
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