Texas Instruments

OMAP-L132 C6-Integra DSP+ARM Processor

Texas Instruments' low-power applications processor based on an ARM926EJ-S™ and C674x DSP core

OMAP-L132 C6-Integra DSP+ARM ProcessorTexas Instruments' OMAP-L132 C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and RISC technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.  

Features
  • Dual Core SoC
    • 200 MHz ARM926EJ-S™ RISC MPU
    • 200 MHz C674x fixed/floating-point VLIW DSP
  • Supports TI's basic secure boot
  • Enhanced direct-memory-access controller (EDMA3)
  • DDR2/mobile DDR memory controller
  • Two multimedia card (MMC)/secure digital (SD) card interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
  • Programmable real-time unit subsystem
  • Three configurable UART modules
  • One multichannel audio serial port
  • Two multichannel buffered serial ports

DSP ARM Processor

AfbeeldingOnderdeelnr. fabrikantBeschrijvingAvailable QuantityPrijs
IC MPU OMAP-L1X 200MHZ 361NFBGAOMAPL132BZWT2IC MPU OMAP-L1X 200MHZ 361NFBGA0 - Immediate
660 - Marketplace		$15.83Details weergeven
Published: 2012-06-29

Related Product Highlight

TMS320C6748, Fixed- and Floating-Point DSPs TI's TMS320C6748 fixed- and floating-point DSPs have development tools that include C compilers, a DSP assembly optimizer, and a Windows® debugger interface.

Related Articles and Blogs

Data Concentrators Combine AFEs MCUs and Radios to Key Smart Grid Efficiency Data concentrators provide the communications lynchpin in automated metering and information systems within smart grid architectures.